1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* -------------------------------------------------- 19 * Errata Workaround for Neoverse N1 Errata 20 * This applies to revision r0p0 and r1p0 of Neoverse N1. 21 * Inputs: 22 * x0: variant[4:7] and revision[0:3] of current cpu. 23 * Shall clobber: x0-x17 24 * -------------------------------------------------- 25 */ 26func errata_n1_1043202_wa 27 /* Compare x0 against revision r1p0 */ 28 mov x17, x30 29 bl check_errata_1043202 30 cbz x0, 1f 31 32 /* Apply instruction patching sequence */ 33 ldr x0, =0x0 34 msr CPUPSELR_EL3, x0 35 ldr x0, =0xF3BF8F2F 36 msr CPUPOR_EL3, x0 37 ldr x0, =0xFFFFFFFF 38 msr CPUPMR_EL3, x0 39 ldr x0, =0x800200071 40 msr CPUPCR_EL3, x0 41 isb 421: 43 ret x17 44endfunc errata_n1_1043202_wa 45 46func check_errata_1043202 47 /* Applies to r0p0 and r1p0 */ 48 mov x1, #0x10 49 b cpu_rev_var_ls 50endfunc check_errata_1043202 51 52func neoverse_n1_reset_func 53 mov x19, x30 54 55 /* Disables speculative loads */ 56 msr SSBS, xzr 57 58 /* Forces all cacheable atomic instructions to be near */ 59 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 60 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 61 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 62 isb 63 64 bl cpu_get_rev_var 65 mov x18, x0 66 67#if ERRATA_N1_1043202 68 mov x0, x18 69 bl errata_n1_1043202_wa 70#endif 71 72#if ENABLE_AMU 73 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 74 mrs x0, actlr_el3 75 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 76 msr actlr_el3, x0 77 isb 78 79 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 80 mrs x0, actlr_el2 81 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 82 msr actlr_el2, x0 83 isb 84 85 /* Enable group0 counters */ 86 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 87 msr CPUAMCNTENSET_EL0, x0 88 isb 89#endif 90 ret x19 91endfunc neoverse_n1_reset_func 92 93 /* --------------------------------------------- 94 * HW will do the cache maintenance while powering down 95 * --------------------------------------------- 96 */ 97func neoverse_n1_core_pwr_dwn 98 /* --------------------------------------------- 99 * Enable CPU power down bit in power control register 100 * --------------------------------------------- 101 */ 102 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 103 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 104 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 105 isb 106 ret 107endfunc neoverse_n1_core_pwr_dwn 108 109#if REPORT_ERRATA 110/* 111 * Errata printing function for Neoverse N1. Must follow AAPCS. 112 */ 113func neoverse_n1_errata_report 114 stp x8, x30, [sp, #-16]! 115 116 bl cpu_get_rev_var 117 mov x8, x0 118 119 /* 120 * Report all errata. The revision-variant information is passed to 121 * checking functions of each errata. 122 */ 123 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 124 125 ldp x8, x30, [sp], #16 126 ret 127endfunc neoverse_n1_errata_report 128#endif 129 130 /* --------------------------------------------- 131 * This function provides neoverse_n1 specific 132 * register information for crash reporting. 133 * It needs to return with x6 pointing to 134 * a list of register names in ascii and 135 * x8 - x15 having values of registers to be 136 * reported. 137 * --------------------------------------------- 138 */ 139.section .rodata.neoverse_n1_regs, "aS" 140neoverse_n1_regs: /* The ascii list of register names to be reported */ 141 .asciz "cpuectlr_el1", "" 142 143func neoverse_n1_cpu_reg_dump 144 adr x6, neoverse_n1_regs 145 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 146 ret 147endfunc neoverse_n1_cpu_reg_dump 148 149declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 150 neoverse_n1_reset_func, \ 151 neoverse_n1_core_pwr_dwn 152