1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23/* -------------------------------------------------- 24 * Errata Workaround for Neoverse N1 Erratum 1043202. 25 * This applies to revision r0p0 and r1p0 of Neoverse N1. 26 * Inputs: 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_n1_1043202_wa 32 /* Compare x0 against revision r1p0 */ 33 mov x17, x30 34 bl check_errata_1043202 35 cbz x0, 1f 36 37 /* Apply instruction patching sequence */ 38 ldr x0, =0x0 39 msr CPUPSELR_EL3, x0 40 ldr x0, =0xF3BF8F2F 41 msr CPUPOR_EL3, x0 42 ldr x0, =0xFFFFFFFF 43 msr CPUPMR_EL3, x0 44 ldr x0, =0x800200071 45 msr CPUPCR_EL3, x0 461: 47 ret x17 48endfunc errata_n1_1043202_wa 49 50func check_errata_1043202 51 /* Applies to r0p0 and r1p0 */ 52 mov x1, #0x10 53 b cpu_rev_var_ls 54endfunc check_errata_1043202 55 56/* -------------------------------------------------- 57 * Disable speculative loads if Neoverse N1 supports 58 * SSBS. 59 * 60 * Shall clobber: x0. 61 * -------------------------------------------------- 62 */ 63func neoverse_n1_disable_speculative_loads 64 /* Check if the PE implements SSBS */ 65 mrs x0, id_aa64pfr1_el1 66 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 67 b.eq 1f 68 69 /* Disable speculative loads */ 70 msr SSBS, xzr 71 721: 73 ret 74endfunc neoverse_n1_disable_speculative_loads 75 76/* -------------------------------------------------- 77 * Errata Workaround for Neoverse N1 Errata #1073348 78 * This applies to revision r0p0 and r1p0 of Neoverse N1. 79 * Inputs: 80 * x0: variant[4:7] and revision[0:3] of current cpu. 81 * Shall clobber: x0-x17 82 * -------------------------------------------------- 83 */ 84func errata_n1_1073348_wa 85 /* Compare x0 against revision r1p0 */ 86 mov x17, x30 87 bl check_errata_1073348 88 cbz x0, 1f 89 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 90 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 91 msr NEOVERSE_N1_CPUACTLR_EL1, x1 921: 93 ret x17 94endfunc errata_n1_1073348_wa 95 96func check_errata_1073348 97 /* Applies to r0p0 and r1p0 */ 98 mov x1, #0x10 99 b cpu_rev_var_ls 100endfunc check_errata_1073348 101 102/* -------------------------------------------------- 103 * Errata Workaround for Neoverse N1 Errata #1130799 104 * This applies to revision <=r2p0 of Neoverse N1. 105 * Inputs: 106 * x0: variant[4:7] and revision[0:3] of current cpu. 107 * Shall clobber: x0-x17 108 * -------------------------------------------------- 109 */ 110func errata_n1_1130799_wa 111 /* Compare x0 against revision r2p0 */ 112 mov x17, x30 113 bl check_errata_1130799 114 cbz x0, 1f 115 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 116 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 117 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1181: 119 ret x17 120endfunc errata_n1_1130799_wa 121 122func check_errata_1130799 123 /* Applies to <=r2p0 */ 124 mov x1, #0x20 125 b cpu_rev_var_ls 126endfunc check_errata_1130799 127 128/* -------------------------------------------------- 129 * Errata Workaround for Neoverse N1 Errata #1165347 130 * This applies to revision <=r2p0 of Neoverse N1. 131 * Inputs: 132 * x0: variant[4:7] and revision[0:3] of current cpu. 133 * Shall clobber: x0-x17 134 * -------------------------------------------------- 135 */ 136func errata_n1_1165347_wa 137 /* Compare x0 against revision r2p0 */ 138 mov x17, x30 139 bl check_errata_1165347 140 cbz x0, 1f 141 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 142 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 143 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 144 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1451: 146 ret x17 147endfunc errata_n1_1165347_wa 148 149func check_errata_1165347 150 /* Applies to <=r2p0 */ 151 mov x1, #0x20 152 b cpu_rev_var_ls 153endfunc check_errata_1165347 154 155/* -------------------------------------------------- 156 * Errata Workaround for Neoverse N1 Errata #1207823 157 * This applies to revision <=r2p0 of Neoverse N1. 158 * Inputs: 159 * x0: variant[4:7] and revision[0:3] of current cpu. 160 * Shall clobber: x0-x17 161 * -------------------------------------------------- 162 */ 163func errata_n1_1207823_wa 164 /* Compare x0 against revision r2p0 */ 165 mov x17, x30 166 bl check_errata_1207823 167 cbz x0, 1f 168 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 169 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 170 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1711: 172 ret x17 173endfunc errata_n1_1207823_wa 174 175func check_errata_1207823 176 /* Applies to <=r2p0 */ 177 mov x1, #0x20 178 b cpu_rev_var_ls 179endfunc check_errata_1207823 180 181/* -------------------------------------------------- 182 * Errata Workaround for Neoverse N1 Errata #1220197 183 * This applies to revision <=r2p0 of Neoverse N1. 184 * Inputs: 185 * x0: variant[4:7] and revision[0:3] of current cpu. 186 * Shall clobber: x0-x17 187 * -------------------------------------------------- 188 */ 189func errata_n1_1220197_wa 190 /* Compare x0 against revision r2p0 */ 191 mov x17, x30 192 bl check_errata_1220197 193 cbz x0, 1f 194 mrs x1, NEOVERSE_N1_CPUECTLR_EL1 195 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK 196 msr NEOVERSE_N1_CPUECTLR_EL1, x1 1971: 198 ret x17 199endfunc errata_n1_1220197_wa 200 201func check_errata_1220197 202 /* Applies to <=r2p0 */ 203 mov x1, #0x20 204 b cpu_rev_var_ls 205endfunc check_errata_1220197 206 207/* -------------------------------------------------- 208 * Errata Workaround for Neoverse N1 Errata #1257314 209 * This applies to revision <=r3p0 of Neoverse N1. 210 * Inputs: 211 * x0: variant[4:7] and revision[0:3] of current cpu. 212 * Shall clobber: x0-x17 213 * -------------------------------------------------- 214 */ 215func errata_n1_1257314_wa 216 /* Compare x0 against revision r3p0 */ 217 mov x17, x30 218 bl check_errata_1257314 219 cbz x0, 1f 220 mrs x1, NEOVERSE_N1_CPUACTLR3_EL1 221 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 222 msr NEOVERSE_N1_CPUACTLR3_EL1, x1 2231: 224 ret x17 225endfunc errata_n1_1257314_wa 226 227func check_errata_1257314 228 /* Applies to <=r3p0 */ 229 mov x1, #0x30 230 b cpu_rev_var_ls 231endfunc check_errata_1257314 232 233/* -------------------------------------------------- 234 * Errata Workaround for Neoverse N1 Errata #1262606 235 * This applies to revision <=r3p0 of Neoverse N1. 236 * Inputs: 237 * x0: variant[4:7] and revision[0:3] of current cpu. 238 * Shall clobber: x0-x17 239 * -------------------------------------------------- 240 */ 241func errata_n1_1262606_wa 242 /* Compare x0 against revision r3p0 */ 243 mov x17, x30 244 bl check_errata_1262606 245 cbz x0, 1f 246 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 247 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 248 msr NEOVERSE_N1_CPUACTLR_EL1, x1 2491: 250 ret x17 251endfunc errata_n1_1262606_wa 252 253func check_errata_1262606 254 /* Applies to <=r3p0 */ 255 mov x1, #0x30 256 b cpu_rev_var_ls 257endfunc check_errata_1262606 258 259/* -------------------------------------------------- 260 * Errata Workaround for Neoverse N1 Errata #1262888 261 * This applies to revision <=r3p0 of Neoverse N1. 262 * Inputs: 263 * x0: variant[4:7] and revision[0:3] of current cpu. 264 * Shall clobber: x0-x17 265 * -------------------------------------------------- 266 */ 267func errata_n1_1262888_wa 268 /* Compare x0 against revision r3p0 */ 269 mov x17, x30 270 bl check_errata_1262888 271 cbz x0, 1f 272 mrs x1, NEOVERSE_N1_CPUECTLR_EL1 273 orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT 274 msr NEOVERSE_N1_CPUECTLR_EL1, x1 2751: 276 ret x17 277endfunc errata_n1_1262888_wa 278 279func check_errata_1262888 280 /* Applies to <=r3p0 */ 281 mov x1, #0x30 282 b cpu_rev_var_ls 283endfunc check_errata_1262888 284 285/* -------------------------------------------------- 286 * Errata Workaround for Neoverse N1 Errata #1275112 287 * This applies to revision <=r3p0 of Neoverse N1. 288 * Inputs: 289 * x0: variant[4:7] and revision[0:3] of current cpu. 290 * Shall clobber: x0-x17 291 * -------------------------------------------------- 292 */ 293func errata_n1_1275112_wa 294 /* Compare x0 against revision r3p0 */ 295 mov x17, x30 296 bl check_errata_1275112 297 cbz x0, 1f 298 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 299 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 300 msr NEOVERSE_N1_CPUACTLR_EL1, x1 3011: 302 ret x17 303endfunc errata_n1_1275112_wa 304 305func check_errata_1275112 306 /* Applies to <=r3p0 */ 307 mov x1, #0x30 308 b cpu_rev_var_ls 309endfunc check_errata_1275112 310 311/* -------------------------------------------------- 312 * Errata Workaround for Neoverse N1 Erratum 1315703. 313 * This applies to revision <= r3p0 of Neoverse N1. 314 * Inputs: 315 * x0: variant[4:7] and revision[0:3] of current cpu. 316 * Shall clobber: x0-x17 317 * -------------------------------------------------- 318 */ 319func errata_n1_1315703_wa 320 /* Compare x0 against revision r3p1 */ 321 mov x17, x30 322 bl check_errata_1315703 323 cbz x0, 1f 324 325 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 326 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 327 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 328 3291: 330 ret x17 331endfunc errata_n1_1315703_wa 332 333func check_errata_1315703 334 /* Applies to everything <= r3p0. */ 335 mov x1, #0x30 336 b cpu_rev_var_ls 337endfunc check_errata_1315703 338 339func neoverse_n1_reset_func 340 mov x19, x30 341 342 bl neoverse_n1_disable_speculative_loads 343 344 /* Forces all cacheable atomic instructions to be near */ 345 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 346 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 347 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 348 isb 349 350 bl cpu_get_rev_var 351 mov x18, x0 352 353#if ERRATA_N1_1043202 354 mov x0, x18 355 bl errata_n1_1043202_wa 356#endif 357 358#if ERRATA_N1_1073348 359 mov x0, x18 360 bl errata_n1_1073348_wa 361#endif 362 363#if ERRATA_N1_1130799 364 mov x0, x18 365 bl errata_n1_1130799_wa 366#endif 367 368#if ERRATA_N1_1165347 369 mov x0, x18 370 bl errata_n1_1165347_wa 371#endif 372 373#if ERRATA_N1_1207823 374 mov x0, x18 375 bl errata_n1_1207823_wa 376#endif 377 378#if ERRATA_N1_1220197 379 mov x0, x18 380 bl errata_n1_1220197_wa 381#endif 382 383#if ERRATA_N1_1257314 384 mov x0, x18 385 bl errata_n1_1257314_wa 386#endif 387 388#if ERRATA_N1_1262606 389 mov x0, x18 390 bl errata_n1_1262606_wa 391#endif 392 393#if ERRATA_N1_1262888 394 mov x0, x18 395 bl errata_n1_1262888_wa 396#endif 397 398#if ERRATA_N1_1275112 399 mov x0, x18 400 bl errata_n1_1275112_wa 401#endif 402 403#if ERRATA_N1_1315703 404 mov x0, x18 405 bl errata_n1_1315703_wa 406#endif 407 408#if ENABLE_AMU 409 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 410 mrs x0, actlr_el3 411 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 412 msr actlr_el3, x0 413 414 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 415 mrs x0, actlr_el2 416 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 417 msr actlr_el2, x0 418 419 /* Enable group0 counters */ 420 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 421 msr CPUAMCNTENSET_EL0, x0 422#endif 423 424#if ERRATA_DSU_936184 425 bl errata_dsu_936184_wa 426#endif 427 428 isb 429 ret x19 430endfunc neoverse_n1_reset_func 431 432 /* --------------------------------------------- 433 * HW will do the cache maintenance while powering down 434 * --------------------------------------------- 435 */ 436func neoverse_n1_core_pwr_dwn 437 /* --------------------------------------------- 438 * Enable CPU power down bit in power control register 439 * --------------------------------------------- 440 */ 441 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 442 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 443 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 444 isb 445 ret 446endfunc neoverse_n1_core_pwr_dwn 447 448#if REPORT_ERRATA 449/* 450 * Errata printing function for Neoverse N1. Must follow AAPCS. 451 */ 452func neoverse_n1_errata_report 453 stp x8, x30, [sp, #-16]! 454 455 bl cpu_get_rev_var 456 mov x8, x0 457 458 /* 459 * Report all errata. The revision-variant information is passed to 460 * checking functions of each errata. 461 */ 462 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 463 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 464 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 465 report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 466 report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 467 report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 468 report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 469 report_errata ERRATA_N1_1262606, neoverse_n1, 1262606 470 report_errata ERRATA_N1_1262888, neoverse_n1, 1262888 471 report_errata ERRATA_N1_1275112, neoverse_n1, 1275112 472 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 473 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 474 475 ldp x8, x30, [sp], #16 476 ret 477endfunc neoverse_n1_errata_report 478#endif 479 480 /* --------------------------------------------- 481 * This function provides neoverse_n1 specific 482 * register information for crash reporting. 483 * It needs to return with x6 pointing to 484 * a list of register names in ascii and 485 * x8 - x15 having values of registers to be 486 * reported. 487 * --------------------------------------------- 488 */ 489.section .rodata.neoverse_n1_regs, "aS" 490neoverse_n1_regs: /* The ascii list of register names to be reported */ 491 .asciz "cpuectlr_el1", "" 492 493func neoverse_n1_cpu_reg_dump 494 adr x6, neoverse_n1_regs 495 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 496 ret 497endfunc neoverse_n1_cpu_reg_dump 498 499declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 500 neoverse_n1_reset_func, \ 501 neoverse_n1_core_pwr_dwn 502