1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23/* -------------------------------------------------- 24 * Errata Workaround for Neoverse N1 Erratum 1043202. 25 * This applies to revision r0p0 and r1p0 of Neoverse N1. 26 * Inputs: 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_n1_1043202_wa 32 /* Compare x0 against revision r1p0 */ 33 mov x17, x30 34 bl check_errata_1043202 35 cbz x0, 1f 36 37 /* Apply instruction patching sequence */ 38 ldr x0, =0x0 39 msr CPUPSELR_EL3, x0 40 ldr x0, =0xF3BF8F2F 41 msr CPUPOR_EL3, x0 42 ldr x0, =0xFFFFFFFF 43 msr CPUPMR_EL3, x0 44 ldr x0, =0x800200071 45 msr CPUPCR_EL3, x0 46 isb 471: 48 ret x17 49endfunc errata_n1_1043202_wa 50 51func check_errata_1043202 52 /* Applies to r0p0 and r1p0 */ 53 mov x1, #0x10 54 b cpu_rev_var_ls 55endfunc check_errata_1043202 56 57/* -------------------------------------------------- 58 * Disable speculative loads if Neoverse N1 supports 59 * SSBS. 60 * 61 * Shall clobber: x0. 62 * -------------------------------------------------- 63 */ 64func neoverse_n1_disable_speculative_loads 65 /* Check if the PE implements SSBS */ 66 mrs x0, id_aa64pfr1_el1 67 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 68 b.eq 1f 69 70 /* Disable speculative loads */ 71 msr SSBS, xzr 72 isb 73 741: 75 ret 76endfunc neoverse_n1_disable_speculative_loads 77 78/* -------------------------------------------------- 79 * Errata Workaround for Neoverse N1 Errata #1073348 80 * This applies to revision r0p0 and r1p0 of Neoverse N1. 81 * Inputs: 82 * x0: variant[4:7] and revision[0:3] of current cpu. 83 * Shall clobber: x0-x17 84 * -------------------------------------------------- 85 */ 86func errata_n1_1073348_wa 87 /* Compare x0 against revision r1p0 */ 88 mov x17, x30 89 bl check_errata_1073348 90 cbz x0, 1f 91 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 92 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 93 msr NEOVERSE_N1_CPUACTLR_EL1, x1 94 isb 951: 96 ret x17 97endfunc errata_n1_1073348_wa 98 99func check_errata_1073348 100 /* Applies to r0p0 and r1p0 */ 101 mov x1, #0x10 102 b cpu_rev_var_ls 103endfunc check_errata_1073348 104 105/* -------------------------------------------------- 106 * Errata Workaround for Neoverse N1 Errata #1130799 107 * This applies to revision <=r2p0 of Neoverse N1. 108 * Inputs: 109 * x0: variant[4:7] and revision[0:3] of current cpu. 110 * Shall clobber: x0-x17 111 * -------------------------------------------------- 112 */ 113func errata_n1_1130799_wa 114 /* Compare x0 against revision r2p0 */ 115 mov x17, x30 116 bl check_errata_1130799 117 cbz x0, 1f 118 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 119 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 120 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 121 isb 1221: 123 ret x17 124endfunc errata_n1_1130799_wa 125 126func check_errata_1130799 127 /* Applies to <=r2p0 */ 128 mov x1, #0x20 129 b cpu_rev_var_ls 130endfunc check_errata_1130799 131 132/* -------------------------------------------------- 133 * Errata Workaround for Neoverse N1 Errata #1165347 134 * This applies to revision <=r2p0 of Neoverse N1. 135 * Inputs: 136 * x0: variant[4:7] and revision[0:3] of current cpu. 137 * Shall clobber: x0-x17 138 * -------------------------------------------------- 139 */ 140func errata_n1_1165347_wa 141 /* Compare x0 against revision r2p0 */ 142 mov x17, x30 143 bl check_errata_1165347 144 cbz x0, 1f 145 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 146 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 147 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 148 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 149 isb 1501: 151 ret x17 152endfunc errata_n1_1165347_wa 153 154func check_errata_1165347 155 /* Applies to <=r2p0 */ 156 mov x1, #0x20 157 b cpu_rev_var_ls 158endfunc check_errata_1165347 159 160/* -------------------------------------------------- 161 * Errata Workaround for Neoverse N1 Errata #1207823 162 * This applies to revision <=r2p0 of Neoverse N1. 163 * Inputs: 164 * x0: variant[4:7] and revision[0:3] of current cpu. 165 * Shall clobber: x0-x17 166 * -------------------------------------------------- 167 */ 168func errata_n1_1207823_wa 169 /* Compare x0 against revision r2p0 */ 170 mov x17, x30 171 bl check_errata_1207823 172 cbz x0, 1f 173 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 174 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 175 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 176 isb 1771: 178 ret x17 179endfunc errata_n1_1207823_wa 180 181func check_errata_1207823 182 /* Applies to <=r2p0 */ 183 mov x1, #0x20 184 b cpu_rev_var_ls 185endfunc check_errata_1207823 186 187/* -------------------------------------------------- 188 * Errata Workaround for Neoverse N1 Erratum 1315703. 189 * This applies to revision <= r3p0 of Neoverse N1. 190 * Inputs: 191 * x0: variant[4:7] and revision[0:3] of current cpu. 192 * Shall clobber: x0-x17 193 * -------------------------------------------------- 194 */ 195func errata_n1_1315703_wa 196 /* Compare x0 against revision r3p1 */ 197 mov x17, x30 198 bl check_errata_1315703 199 cbz x0, 1f 200 201 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 202 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 203 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 204 isb 205 2061: 207 ret x17 208endfunc errata_n1_1315703_wa 209 210func check_errata_1315703 211 /* Applies to everything <= r3p0. */ 212 mov x1, #0x30 213 b cpu_rev_var_ls 214endfunc check_errata_1315703 215 216func neoverse_n1_reset_func 217 mov x19, x30 218 219 bl neoverse_n1_disable_speculative_loads 220 221 /* Forces all cacheable atomic instructions to be near */ 222 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 223 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 224 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 225 isb 226 227 bl cpu_get_rev_var 228 mov x18, x0 229 230#if ERRATA_N1_1043202 231 mov x0, x18 232 bl errata_n1_1043202_wa 233#endif 234 235#if ERRATA_N1_1073348 236 mov x0, x18 237 bl errata_n1_1073348_wa 238#endif 239 240#if ERRATA_N1_1130799 241 mov x0, x18 242 bl errata_n1_1130799_wa 243#endif 244 245#if ERRATA_N1_1165347 246 mov x0, x18 247 bl errata_n1_1165347_wa 248#endif 249 250#if ERRATA_N1_1207823 251 mov x0, x18 252 bl errata_n1_1207823_wa 253#endif 254 255#if ERRATA_N1_1315703 256 mov x0, x18 257 bl errata_n1_1315703_wa 258#endif 259 260#if ENABLE_AMU 261 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 262 mrs x0, actlr_el3 263 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 264 msr actlr_el3, x0 265 isb 266 267 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 268 mrs x0, actlr_el2 269 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 270 msr actlr_el2, x0 271 isb 272 273 /* Enable group0 counters */ 274 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 275 msr CPUAMCNTENSET_EL0, x0 276 isb 277#endif 278 279#if ERRATA_DSU_936184 280 bl errata_dsu_936184_wa 281#endif 282 283 ret x19 284endfunc neoverse_n1_reset_func 285 286 /* --------------------------------------------- 287 * HW will do the cache maintenance while powering down 288 * --------------------------------------------- 289 */ 290func neoverse_n1_core_pwr_dwn 291 /* --------------------------------------------- 292 * Enable CPU power down bit in power control register 293 * --------------------------------------------- 294 */ 295 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 296 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 297 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 298 isb 299 ret 300endfunc neoverse_n1_core_pwr_dwn 301 302#if REPORT_ERRATA 303/* 304 * Errata printing function for Neoverse N1. Must follow AAPCS. 305 */ 306func neoverse_n1_errata_report 307 stp x8, x30, [sp, #-16]! 308 309 bl cpu_get_rev_var 310 mov x8, x0 311 312 /* 313 * Report all errata. The revision-variant information is passed to 314 * checking functions of each errata. 315 */ 316 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 317 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 318 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 319 report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 320 report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 321 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 322 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 323 324 ldp x8, x30, [sp], #16 325 ret 326endfunc neoverse_n1_errata_report 327#endif 328 329 /* --------------------------------------------- 330 * This function provides neoverse_n1 specific 331 * register information for crash reporting. 332 * It needs to return with x6 pointing to 333 * a list of register names in ascii and 334 * x8 - x15 having values of registers to be 335 * reported. 336 * --------------------------------------------- 337 */ 338.section .rodata.neoverse_n1_regs, "aS" 339neoverse_n1_regs: /* The ascii list of register names to be reported */ 340 .asciz "cpuectlr_el1", "" 341 342func neoverse_n1_cpu_reg_dump 343 adr x6, neoverse_n1_regs 344 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 345 ret 346endfunc neoverse_n1_cpu_reg_dump 347 348declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 349 neoverse_n1_reset_func, \ 350 neoverse_n1_core_pwr_dwn 351