1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23/* -------------------------------------------------- 24 * Errata Workaround for Neoverse N1 Erratum 1043202. 25 * This applies to revision r0p0 and r1p0 of Neoverse N1. 26 * Inputs: 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_n1_1043202_wa 32 /* Compare x0 against revision r1p0 */ 33 mov x17, x30 34 bl check_errata_1043202 35 cbz x0, 1f 36 37 /* Apply instruction patching sequence */ 38 ldr x0, =0x0 39 msr CPUPSELR_EL3, x0 40 ldr x0, =0xF3BF8F2F 41 msr CPUPOR_EL3, x0 42 ldr x0, =0xFFFFFFFF 43 msr CPUPMR_EL3, x0 44 ldr x0, =0x800200071 45 msr CPUPCR_EL3, x0 46 isb 471: 48 ret x17 49endfunc errata_n1_1043202_wa 50 51func check_errata_1043202 52 /* Applies to r0p0 and r1p0 */ 53 mov x1, #0x10 54 b cpu_rev_var_ls 55endfunc check_errata_1043202 56 57/* -------------------------------------------------- 58 * Disable speculative loads if Neoverse N1 supports 59 * SSBS. 60 * 61 * Shall clobber: x0. 62 * -------------------------------------------------- 63 */ 64func neoverse_n1_disable_speculative_loads 65 /* Check if the PE implements SSBS */ 66 mrs x0, id_aa64pfr1_el1 67 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 68 b.eq 1f 69 70 /* Disable speculative loads */ 71 msr SSBS, xzr 72 isb 73 741: 75 ret 76endfunc neoverse_n1_disable_speculative_loads 77 78/* -------------------------------------------------- 79 * Errata Workaround for Neoverse N1 Errata #1073348 80 * This applies to revision r0p0 and r1p0 of Neoverse N1. 81 * Inputs: 82 * x0: variant[4:7] and revision[0:3] of current cpu. 83 * Shall clobber: x0-x17 84 * -------------------------------------------------- 85 */ 86func errata_n1_1073348_wa 87 /* Compare x0 against revision r1p0 */ 88 mov x17, x30 89 bl check_errata_1073348 90 cbz x0, 1f 91 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 92 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 93 msr NEOVERSE_N1_CPUACTLR_EL1, x1 94 isb 951: 96 ret x17 97endfunc errata_n1_1073348_wa 98 99func check_errata_1073348 100 /* Applies to r0p0 and r1p0 */ 101 mov x1, #0x10 102 b cpu_rev_var_ls 103endfunc check_errata_1073348 104 105/* -------------------------------------------------- 106 * Errata Workaround for Neoverse N1 Errata #1130799 107 * This applies to revision <=r2p0 of Neoverse N1. 108 * Inputs: 109 * x0: variant[4:7] and revision[0:3] of current cpu. 110 * Shall clobber: x0-x17 111 * -------------------------------------------------- 112 */ 113func errata_n1_1130799_wa 114 /* Compare x0 against revision r2p0 */ 115 mov x17, x30 116 bl check_errata_1130799 117 cbz x0, 1f 118 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 119 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 120 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 121 isb 1221: 123 ret x17 124endfunc errata_n1_1130799_wa 125 126func check_errata_1130799 127 /* Applies to <=r2p0 */ 128 mov x1, #0x20 129 b cpu_rev_var_ls 130endfunc check_errata_1130799 131 132/* -------------------------------------------------- 133 * Errata Workaround for Neoverse N1 Erratum 1315703. 134 * This applies to revision <= r3p0 of Neoverse N1. 135 * Inputs: 136 * x0: variant[4:7] and revision[0:3] of current cpu. 137 * Shall clobber: x0-x17 138 * -------------------------------------------------- 139 */ 140func errata_n1_1315703_wa 141 /* Compare x0 against revision r3p1 */ 142 mov x17, x30 143 bl check_errata_1315703 144 cbz x0, 1f 145 146 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 147 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 148 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 149 isb 150 1511: 152 ret x17 153endfunc errata_n1_1315703_wa 154 155func check_errata_1315703 156 /* Applies to everything <= r3p0. */ 157 mov x1, #0x30 158 b cpu_rev_var_ls 159endfunc check_errata_1315703 160 161func neoverse_n1_reset_func 162 mov x19, x30 163 164 bl neoverse_n1_disable_speculative_loads 165 166 /* Forces all cacheable atomic instructions to be near */ 167 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 168 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 169 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 170 isb 171 172 bl cpu_get_rev_var 173 mov x18, x0 174 175#if ERRATA_N1_1043202 176 mov x0, x18 177 bl errata_n1_1043202_wa 178#endif 179 180#if ERRATA_N1_1073348 181 mov x0, x18 182 bl errata_n1_1073348_wa 183#endif 184 185#if ERRATA_N1_1130799 186 mov x0, x18 187 bl errata_n1_1130799_wa 188#endif 189 190#if ERRATA_N1_1315703 191 mov x0, x18 192 bl errata_n1_1315703_wa 193#endif 194 195#if ENABLE_AMU 196 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 197 mrs x0, actlr_el3 198 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 199 msr actlr_el3, x0 200 isb 201 202 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 203 mrs x0, actlr_el2 204 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 205 msr actlr_el2, x0 206 isb 207 208 /* Enable group0 counters */ 209 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 210 msr CPUAMCNTENSET_EL0, x0 211 isb 212#endif 213 214#if ERRATA_DSU_936184 215 bl errata_dsu_936184_wa 216#endif 217 218 ret x19 219endfunc neoverse_n1_reset_func 220 221 /* --------------------------------------------- 222 * HW will do the cache maintenance while powering down 223 * --------------------------------------------- 224 */ 225func neoverse_n1_core_pwr_dwn 226 /* --------------------------------------------- 227 * Enable CPU power down bit in power control register 228 * --------------------------------------------- 229 */ 230 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 231 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 232 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 233 isb 234 ret 235endfunc neoverse_n1_core_pwr_dwn 236 237#if REPORT_ERRATA 238/* 239 * Errata printing function for Neoverse N1. Must follow AAPCS. 240 */ 241func neoverse_n1_errata_report 242 stp x8, x30, [sp, #-16]! 243 244 bl cpu_get_rev_var 245 mov x8, x0 246 247 /* 248 * Report all errata. The revision-variant information is passed to 249 * checking functions of each errata. 250 */ 251 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 252 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 253 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 254 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 255 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 256 257 ldp x8, x30, [sp], #16 258 ret 259endfunc neoverse_n1_errata_report 260#endif 261 262 /* --------------------------------------------- 263 * This function provides neoverse_n1 specific 264 * register information for crash reporting. 265 * It needs to return with x6 pointing to 266 * a list of register names in ascii and 267 * x8 - x15 having values of registers to be 268 * reported. 269 * --------------------------------------------- 270 */ 271.section .rodata.neoverse_n1_regs, "aS" 272neoverse_n1_regs: /* The ascii list of register names to be reported */ 273 .asciz "cpuectlr_el1", "" 274 275func neoverse_n1_cpu_reg_dump 276 adr x6, neoverse_n1_regs 277 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 278 ret 279endfunc neoverse_n1_cpu_reg_dump 280 281declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 282 neoverse_n1_reset_func, \ 283 neoverse_n1_core_pwr_dwn 284