1/* 2 * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpuamu.h> 10#include <cpu_macros.S> 11#include <neoverse_n1.h> 12#include "wa_cve_2022_23960_bhb_vector.S" 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 .global neoverse_n1_errata_ic_trap_handler 25 26#if WORKAROUND_CVE_2022_23960 27 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1 28#endif /* WORKAROUND_CVE_2022_23960 */ 29 30/* -------------------------------------------------- 31 * Errata Workaround for Neoverse N1 Erratum 1043202. 32 * This applies to revision r0p0 and r1p0 of Neoverse N1. 33 * Inputs: 34 * x0: variant[4:7] and revision[0:3] of current cpu. 35 * Shall clobber: x0-x17 36 * -------------------------------------------------- 37 */ 38func errata_n1_1043202_wa 39 /* Compare x0 against revision r1p0 */ 40 mov x17, x30 41 bl check_errata_1043202 42 cbz x0, 1f 43 44 /* Apply instruction patching sequence */ 45 ldr x0, =0x0 46 msr CPUPSELR_EL3, x0 47 ldr x0, =0xF3BF8F2F 48 msr CPUPOR_EL3, x0 49 ldr x0, =0xFFFFFFFF 50 msr CPUPMR_EL3, x0 51 ldr x0, =0x800200071 52 msr CPUPCR_EL3, x0 53 isb 541: 55 ret x17 56endfunc errata_n1_1043202_wa 57 58func check_errata_1043202 59 /* Applies to r0p0 and r1p0 */ 60 mov x1, #0x10 61 b cpu_rev_var_ls 62endfunc check_errata_1043202 63 64/* -------------------------------------------------- 65 * Disable speculative loads if Neoverse N1 supports 66 * SSBS. 67 * 68 * Shall clobber: x0. 69 * -------------------------------------------------- 70 */ 71func neoverse_n1_disable_speculative_loads 72 /* Check if the PE implements SSBS */ 73 mrs x0, id_aa64pfr1_el1 74 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 75 b.eq 1f 76 77 /* Disable speculative loads */ 78 msr SSBS, xzr 79 801: 81 ret 82endfunc neoverse_n1_disable_speculative_loads 83 84/* -------------------------------------------------- 85 * Errata Workaround for Neoverse N1 Errata #1073348 86 * This applies to revision r0p0 and r1p0 of Neoverse N1. 87 * Inputs: 88 * x0: variant[4:7] and revision[0:3] of current cpu. 89 * Shall clobber: x0-x17 90 * -------------------------------------------------- 91 */ 92func errata_n1_1073348_wa 93 /* Compare x0 against revision r1p0 */ 94 mov x17, x30 95 bl check_errata_1073348 96 cbz x0, 1f 97 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 98 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 99 msr NEOVERSE_N1_CPUACTLR_EL1, x1 1001: 101 ret x17 102endfunc errata_n1_1073348_wa 103 104func check_errata_1073348 105 /* Applies to r0p0 and r1p0 */ 106 mov x1, #0x10 107 b cpu_rev_var_ls 108endfunc check_errata_1073348 109 110/* -------------------------------------------------- 111 * Errata Workaround for Neoverse N1 Errata #1130799 112 * This applies to revision <=r2p0 of Neoverse N1. 113 * Inputs: 114 * x0: variant[4:7] and revision[0:3] of current cpu. 115 * Shall clobber: x0-x17 116 * -------------------------------------------------- 117 */ 118func errata_n1_1130799_wa 119 /* Compare x0 against revision r2p0 */ 120 mov x17, x30 121 bl check_errata_1130799 122 cbz x0, 1f 123 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 124 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 125 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1261: 127 ret x17 128endfunc errata_n1_1130799_wa 129 130func check_errata_1130799 131 /* Applies to <=r2p0 */ 132 mov x1, #0x20 133 b cpu_rev_var_ls 134endfunc check_errata_1130799 135 136/* -------------------------------------------------- 137 * Errata Workaround for Neoverse N1 Errata #1165347 138 * This applies to revision <=r2p0 of Neoverse N1. 139 * Inputs: 140 * x0: variant[4:7] and revision[0:3] of current cpu. 141 * Shall clobber: x0-x17 142 * -------------------------------------------------- 143 */ 144func errata_n1_1165347_wa 145 /* Compare x0 against revision r2p0 */ 146 mov x17, x30 147 bl check_errata_1165347 148 cbz x0, 1f 149 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 150 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 151 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 152 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1531: 154 ret x17 155endfunc errata_n1_1165347_wa 156 157func check_errata_1165347 158 /* Applies to <=r2p0 */ 159 mov x1, #0x20 160 b cpu_rev_var_ls 161endfunc check_errata_1165347 162 163/* -------------------------------------------------- 164 * Errata Workaround for Neoverse N1 Errata #1207823 165 * This applies to revision <=r2p0 of Neoverse N1. 166 * Inputs: 167 * x0: variant[4:7] and revision[0:3] of current cpu. 168 * Shall clobber: x0-x17 169 * -------------------------------------------------- 170 */ 171func errata_n1_1207823_wa 172 /* Compare x0 against revision r2p0 */ 173 mov x17, x30 174 bl check_errata_1207823 175 cbz x0, 1f 176 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 177 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 178 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 1791: 180 ret x17 181endfunc errata_n1_1207823_wa 182 183func check_errata_1207823 184 /* Applies to <=r2p0 */ 185 mov x1, #0x20 186 b cpu_rev_var_ls 187endfunc check_errata_1207823 188 189/* -------------------------------------------------- 190 * Errata Workaround for Neoverse N1 Errata #1220197 191 * This applies to revision <=r2p0 of Neoverse N1. 192 * Inputs: 193 * x0: variant[4:7] and revision[0:3] of current cpu. 194 * Shall clobber: x0-x17 195 * -------------------------------------------------- 196 */ 197func errata_n1_1220197_wa 198 /* Compare x0 against revision r2p0 */ 199 mov x17, x30 200 bl check_errata_1220197 201 cbz x0, 1f 202 mrs x1, NEOVERSE_N1_CPUECTLR_EL1 203 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK 204 msr NEOVERSE_N1_CPUECTLR_EL1, x1 2051: 206 ret x17 207endfunc errata_n1_1220197_wa 208 209func check_errata_1220197 210 /* Applies to <=r2p0 */ 211 mov x1, #0x20 212 b cpu_rev_var_ls 213endfunc check_errata_1220197 214 215/* -------------------------------------------------- 216 * Errata Workaround for Neoverse N1 Errata #1257314 217 * This applies to revision <=r3p0 of Neoverse N1. 218 * Inputs: 219 * x0: variant[4:7] and revision[0:3] of current cpu. 220 * Shall clobber: x0-x17 221 * -------------------------------------------------- 222 */ 223func errata_n1_1257314_wa 224 /* Compare x0 against revision r3p0 */ 225 mov x17, x30 226 bl check_errata_1257314 227 cbz x0, 1f 228 mrs x1, NEOVERSE_N1_CPUACTLR3_EL1 229 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 230 msr NEOVERSE_N1_CPUACTLR3_EL1, x1 2311: 232 ret x17 233endfunc errata_n1_1257314_wa 234 235func check_errata_1257314 236 /* Applies to <=r3p0 */ 237 mov x1, #0x30 238 b cpu_rev_var_ls 239endfunc check_errata_1257314 240 241/* -------------------------------------------------- 242 * Errata Workaround for Neoverse N1 Errata #1262606 243 * This applies to revision <=r3p0 of Neoverse N1. 244 * Inputs: 245 * x0: variant[4:7] and revision[0:3] of current cpu. 246 * Shall clobber: x0-x17 247 * -------------------------------------------------- 248 */ 249func errata_n1_1262606_wa 250 /* Compare x0 against revision r3p0 */ 251 mov x17, x30 252 bl check_errata_1262606 253 cbz x0, 1f 254 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 255 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 256 msr NEOVERSE_N1_CPUACTLR_EL1, x1 2571: 258 ret x17 259endfunc errata_n1_1262606_wa 260 261func check_errata_1262606 262 /* Applies to <=r3p0 */ 263 mov x1, #0x30 264 b cpu_rev_var_ls 265endfunc check_errata_1262606 266 267/* -------------------------------------------------- 268 * Errata Workaround for Neoverse N1 Errata #1262888 269 * This applies to revision <=r3p0 of Neoverse N1. 270 * Inputs: 271 * x0: variant[4:7] and revision[0:3] of current cpu. 272 * Shall clobber: x0-x17 273 * -------------------------------------------------- 274 */ 275func errata_n1_1262888_wa 276 /* Compare x0 against revision r3p0 */ 277 mov x17, x30 278 bl check_errata_1262888 279 cbz x0, 1f 280 mrs x1, NEOVERSE_N1_CPUECTLR_EL1 281 orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT 282 msr NEOVERSE_N1_CPUECTLR_EL1, x1 2831: 284 ret x17 285endfunc errata_n1_1262888_wa 286 287func check_errata_1262888 288 /* Applies to <=r3p0 */ 289 mov x1, #0x30 290 b cpu_rev_var_ls 291endfunc check_errata_1262888 292 293/* -------------------------------------------------- 294 * Errata Workaround for Neoverse N1 Errata #1275112 295 * This applies to revision <=r3p0 of Neoverse N1. 296 * Inputs: 297 * x0: variant[4:7] and revision[0:3] of current cpu. 298 * Shall clobber: x0-x17 299 * -------------------------------------------------- 300 */ 301func errata_n1_1275112_wa 302 /* Compare x0 against revision r3p0 */ 303 mov x17, x30 304 bl check_errata_1275112 305 cbz x0, 1f 306 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 307 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 308 msr NEOVERSE_N1_CPUACTLR_EL1, x1 3091: 310 ret x17 311endfunc errata_n1_1275112_wa 312 313func check_errata_1275112 314 /* Applies to <=r3p0 */ 315 mov x1, #0x30 316 b cpu_rev_var_ls 317endfunc check_errata_1275112 318 319/* -------------------------------------------------- 320 * Errata Workaround for Neoverse N1 Erratum 1315703. 321 * This applies to revision <= r3p0 of Neoverse N1. 322 * Inputs: 323 * x0: variant[4:7] and revision[0:3] of current cpu. 324 * Shall clobber: x0-x17 325 * -------------------------------------------------- 326 */ 327func errata_n1_1315703_wa 328 /* Compare x0 against revision r3p1 */ 329 mov x17, x30 330 bl check_errata_1315703 331 cbz x0, 1f 332 333 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 334 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 335 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 336 3371: 338 ret x17 339endfunc errata_n1_1315703_wa 340 341func check_errata_1315703 342 /* Applies to everything <= r3p0. */ 343 mov x1, #0x30 344 b cpu_rev_var_ls 345endfunc check_errata_1315703 346 347/* -------------------------------------------------- 348 * Errata Workaround for Neoverse N1 Erratum 1542419. 349 * This applies to revisions r3p0 - r4p0 of Neoverse N1 350 * Inputs: 351 * x0: variant[4:7] and revision[0:3] of current cpu. 352 * Shall clobber: x0-x17 353 * -------------------------------------------------- 354 */ 355func errata_n1_1542419_wa 356 /* Compare x0 against revision r3p0 and r4p0 */ 357 mov x17, x30 358 bl check_errata_1542419 359 cbz x0, 1f 360 361 /* Apply instruction patching sequence */ 362 ldr x0, =0x0 363 msr CPUPSELR_EL3, x0 364 ldr x0, =0xEE670D35 365 msr CPUPOR_EL3, x0 366 ldr x0, =0xFFFF0FFF 367 msr CPUPMR_EL3, x0 368 ldr x0, =0x08000020007D 369 msr CPUPCR_EL3, x0 370 isb 3711: 372 ret x17 373endfunc errata_n1_1542419_wa 374 375func check_errata_1542419 376 /* Applies to everything r3p0 - r4p0. */ 377 mov x1, #0x30 378 mov x2, #0x40 379 b cpu_rev_var_range 380endfunc check_errata_1542419 381 382 /* -------------------------------------------------- 383 * Errata Workaround for Neoverse N1 Errata #1868343. 384 * This applies to revision <= r4p0 of Neoverse N1. 385 * This workaround is the same as the workaround for 386 * errata 1262606 and 1275112 but applies to a wider 387 * revision range. 388 * Inputs: 389 * x0: variant[4:7] and revision[0:3] of current cpu. 390 * Shall clobber: x0-x17 391 * -------------------------------------------------- 392 */ 393func errata_n1_1868343_wa 394 /* 395 * Compare x0 against revision r4p0 396 */ 397 mov x17, x30 398 bl check_errata_1868343 399 cbz x0, 1f 400 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 401 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 402 msr NEOVERSE_N1_CPUACTLR_EL1, x1 403 isb 4041: 405 ret x17 406endfunc errata_n1_1868343_wa 407 408func check_errata_1868343 409 /* Applies to everything <= r4p0 */ 410 mov x1, #0x40 411 b cpu_rev_var_ls 412endfunc check_errata_1868343 413 414 /* -------------------------------------------------- 415 * Errata Workaround for Neoverse N1 Errata #1946160. 416 * This applies to revisions r3p0, r3p1, r4p0, and 417 * r4p1 of Neoverse N1. It also exists in r0p0, r1p0, 418 * and r2p0 but there is no fix in these revisions. 419 * Inputs: 420 * x0: variant[4:7] and revision[0:3] of current cpu. 421 * Shall clobber: x0-x17 422 * -------------------------------------------------- 423 */ 424func errata_n1_1946160_wa 425 /* 426 * Compare x0 against r3p0 - r4p1 427 */ 428 mov x17, x30 429 bl check_errata_1946160 430 cbz x0, 1f 431 432 mov x0, #3 433 msr S3_6_C15_C8_0, x0 434 ldr x0, =0x10E3900002 435 msr S3_6_C15_C8_2, x0 436 ldr x0, =0x10FFF00083 437 msr S3_6_C15_C8_3, x0 438 ldr x0, =0x2001003FF 439 msr S3_6_C15_C8_1, x0 440 441 mov x0, #4 442 msr S3_6_C15_C8_0, x0 443 ldr x0, =0x10E3800082 444 msr S3_6_C15_C8_2, x0 445 ldr x0, =0x10FFF00083 446 msr S3_6_C15_C8_3, x0 447 ldr x0, =0x2001003FF 448 msr S3_6_C15_C8_1, x0 449 450 mov x0, #5 451 msr S3_6_C15_C8_0, x0 452 ldr x0, =0x10E3800200 453 msr S3_6_C15_C8_2, x0 454 ldr x0, =0x10FFF003E0 455 msr S3_6_C15_C8_3, x0 456 ldr x0, =0x2001003FF 457 msr S3_6_C15_C8_1, x0 458 459 isb 4601: 461 ret x17 462endfunc errata_n1_1946160_wa 463 464func check_errata_1946160 465 /* Applies to r3p0 - r4p1. */ 466 mov x1, #0x30 467 mov x2, #0x41 468 b cpu_rev_var_range 469endfunc check_errata_1946160 470 471func check_errata_cve_2022_23960 472#if WORKAROUND_CVE_2022_23960 473 mov x0, #ERRATA_APPLIES 474#else 475 mov x0, #ERRATA_MISSING 476#endif 477 ret 478endfunc check_errata_cve_2022_23960 479 480func neoverse_n1_reset_func 481 mov x19, x30 482 483 bl neoverse_n1_disable_speculative_loads 484 485 /* Forces all cacheable atomic instructions to be near */ 486 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 487 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 488 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 489 isb 490 491 bl cpu_get_rev_var 492 mov x18, x0 493 494#if ERRATA_N1_1043202 495 mov x0, x18 496 bl errata_n1_1043202_wa 497#endif 498 499#if ERRATA_N1_1073348 500 mov x0, x18 501 bl errata_n1_1073348_wa 502#endif 503 504#if ERRATA_N1_1130799 505 mov x0, x18 506 bl errata_n1_1130799_wa 507#endif 508 509#if ERRATA_N1_1165347 510 mov x0, x18 511 bl errata_n1_1165347_wa 512#endif 513 514#if ERRATA_N1_1207823 515 mov x0, x18 516 bl errata_n1_1207823_wa 517#endif 518 519#if ERRATA_N1_1220197 520 mov x0, x18 521 bl errata_n1_1220197_wa 522#endif 523 524#if ERRATA_N1_1257314 525 mov x0, x18 526 bl errata_n1_1257314_wa 527#endif 528 529#if ERRATA_N1_1262606 530 mov x0, x18 531 bl errata_n1_1262606_wa 532#endif 533 534#if ERRATA_N1_1262888 535 mov x0, x18 536 bl errata_n1_1262888_wa 537#endif 538 539#if ERRATA_N1_1275112 540 mov x0, x18 541 bl errata_n1_1275112_wa 542#endif 543 544#if ERRATA_N1_1315703 545 mov x0, x18 546 bl errata_n1_1315703_wa 547#endif 548 549#if ERRATA_N1_1542419 550 mov x0, x18 551 bl errata_n1_1542419_wa 552#endif 553 554#if ERRATA_N1_1868343 555 mov x0, x18 556 bl errata_n1_1868343_wa 557#endif 558 559#if ERRATA_N1_1946160 560 mov x0, x18 561 bl errata_n1_1946160_wa 562#endif 563 564#if ENABLE_AMU 565 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 566 mrs x0, actlr_el3 567 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 568 msr actlr_el3, x0 569 570 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 571 mrs x0, actlr_el2 572 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 573 msr actlr_el2, x0 574 575 /* Enable group0 counters */ 576 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 577 msr CPUAMCNTENSET_EL0, x0 578#endif 579 580#if NEOVERSE_Nx_EXTERNAL_LLC 581 /* Some system may have External LLC, core needs to be made aware */ 582 mrs x0, NEOVERSE_N1_CPUECTLR_EL1 583 orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT 584 msr NEOVERSE_N1_CPUECTLR_EL1, x0 585#endif 586 587#if ERRATA_DSU_936184 588 bl errata_dsu_936184_wa 589#endif 590 591#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 592 /* 593 * The Neoverse-N1 generic vectors are overridden to apply errata 594 * mitigation on exception entry from lower ELs. 595 */ 596 adr x0, wa_cve_vbar_neoverse_n1 597 msr vbar_el3, x0 598#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 599 600 isb 601 ret x19 602endfunc neoverse_n1_reset_func 603 604 /* --------------------------------------------- 605 * HW will do the cache maintenance while powering down 606 * --------------------------------------------- 607 */ 608func neoverse_n1_core_pwr_dwn 609 /* --------------------------------------------- 610 * Enable CPU power down bit in power control register 611 * --------------------------------------------- 612 */ 613 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 614 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 615 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 616 isb 617 ret 618endfunc neoverse_n1_core_pwr_dwn 619 620#if REPORT_ERRATA 621/* 622 * Errata printing function for Neoverse N1. Must follow AAPCS. 623 */ 624func neoverse_n1_errata_report 625 stp x8, x30, [sp, #-16]! 626 627 bl cpu_get_rev_var 628 mov x8, x0 629 630 /* 631 * Report all errata. The revision-variant information is passed to 632 * checking functions of each errata. 633 */ 634 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 635 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 636 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 637 report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 638 report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 639 report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 640 report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 641 report_errata ERRATA_N1_1262606, neoverse_n1, 1262606 642 report_errata ERRATA_N1_1262888, neoverse_n1, 1262888 643 report_errata ERRATA_N1_1275112, neoverse_n1, 1275112 644 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 645 report_errata ERRATA_N1_1542419, neoverse_n1, 1542419 646 report_errata ERRATA_N1_1868343, neoverse_n1, 1868343 647 report_errata ERRATA_N1_1946160, neoverse_n1, 1946160 648 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 649 report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960 650 651 ldp x8, x30, [sp], #16 652 ret 653endfunc neoverse_n1_errata_report 654#endif 655 656/* 657 * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB 658 * inner-shareable invalidation to an arbitrary address followed by a DSB. 659 * 660 * x1: Exception Syndrome 661 */ 662func neoverse_n1_errata_ic_trap_handler 663 cmp x1, #NEOVERSE_N1_EC_IC_TRAP 664 b.ne 1f 665 tlbi vae3is, xzr 666 dsb sy 667 668 # Skip the IC instruction itself 669 mrs x3, elr_el3 670 add x3, x3, #4 671 msr elr_el3, x3 672 673 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 674 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 675 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 676 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 677 678#if IMAGE_BL31 && RAS_EXTENSION 679 /* 680 * Issue Error Synchronization Barrier to synchronize SErrors before 681 * exiting EL3. We're running with EAs unmasked, so any synchronized 682 * errors would be taken immediately; therefore no need to inspect 683 * DISR_EL1 register. 684 */ 685 esb 686#endif 687 exception_return 6881: 689 ret 690endfunc neoverse_n1_errata_ic_trap_handler 691 692 /* --------------------------------------------- 693 * This function provides neoverse_n1 specific 694 * register information for crash reporting. 695 * It needs to return with x6 pointing to 696 * a list of register names in ascii and 697 * x8 - x15 having values of registers to be 698 * reported. 699 * --------------------------------------------- 700 */ 701.section .rodata.neoverse_n1_regs, "aS" 702neoverse_n1_regs: /* The ascii list of register names to be reported */ 703 .asciz "cpuectlr_el1", "" 704 705func neoverse_n1_cpu_reg_dump 706 adr x6, neoverse_n1_regs 707 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 708 ret 709endfunc neoverse_n1_cpu_reg_dump 710 711declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \ 712 neoverse_n1_reset_func, \ 713 neoverse_n1_errata_ic_trap_handler, \ 714 neoverse_n1_core_pwr_dwn 715