1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23/* -------------------------------------------------- 24 * Errata Workaround for Neoverse N1 Erratum 1043202. 25 * This applies to revision r0p0 and r1p0 of Neoverse N1. 26 * Inputs: 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_n1_1043202_wa 32 /* Compare x0 against revision r1p0 */ 33 mov x17, x30 34 bl check_errata_1043202 35 cbz x0, 1f 36 37 /* Apply instruction patching sequence */ 38 ldr x0, =0x0 39 msr CPUPSELR_EL3, x0 40 ldr x0, =0xF3BF8F2F 41 msr CPUPOR_EL3, x0 42 ldr x0, =0xFFFFFFFF 43 msr CPUPMR_EL3, x0 44 ldr x0, =0x800200071 45 msr CPUPCR_EL3, x0 46 isb 471: 48 ret x17 49endfunc errata_n1_1043202_wa 50 51func check_errata_1043202 52 /* Applies to r0p0 and r1p0 */ 53 mov x1, #0x10 54 b cpu_rev_var_ls 55endfunc check_errata_1043202 56 57/* -------------------------------------------------- 58 * Disable speculative loads if Neoverse N1 supports 59 * SSBS. 60 * 61 * Shall clobber: x0. 62 * -------------------------------------------------- 63 */ 64func neoverse_n1_disable_speculative_loads 65 /* Check if the PE implements SSBS */ 66 mrs x0, id_aa64pfr1_el1 67 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 68 b.eq 1f 69 70 /* Disable speculative loads */ 71 msr SSBS, xzr 72 isb 73 741: 75 ret 76endfunc neoverse_n1_disable_speculative_loads 77 78/* -------------------------------------------------- 79 * Errata Workaround for Neoverse N1 Erratum 1315703. 80 * This applies to revision <= r3p0 of Neoverse N1. 81 * Inputs: 82 * x0: variant[4:7] and revision[0:3] of current cpu. 83 * Shall clobber: x0-x17 84 * -------------------------------------------------- 85 */ 86func errata_n1_1315703_wa 87 /* Compare x0 against revision r3p1 */ 88 mov x17, x30 89 bl check_errata_1315703 90 cbz x0, 1f 91 92 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 93 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 94 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 95 isb 96 971: 98 ret x17 99endfunc errata_n1_1315703_wa 100 101func check_errata_1315703 102 /* Applies to everything <= r3p0. */ 103 mov x1, #0x30 104 b cpu_rev_var_ls 105endfunc check_errata_1315703 106 107func neoverse_n1_reset_func 108 mov x19, x30 109 110 bl neoverse_n1_disable_speculative_loads 111 112 /* Forces all cacheable atomic instructions to be near */ 113 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 114 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 115 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 116 isb 117 118 bl cpu_get_rev_var 119 mov x18, x0 120 121#if ERRATA_N1_1043202 122 mov x0, x18 123 bl errata_n1_1043202_wa 124#endif 125 126#if ERRATA_N1_1315703 127 mov x0, x18 128 bl errata_n1_1315703_wa 129#endif 130 131#if ENABLE_AMU 132 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 133 mrs x0, actlr_el3 134 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 135 msr actlr_el3, x0 136 isb 137 138 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 139 mrs x0, actlr_el2 140 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 141 msr actlr_el2, x0 142 isb 143 144 /* Enable group0 counters */ 145 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 146 msr CPUAMCNTENSET_EL0, x0 147 isb 148#endif 149 150#if ERRATA_DSU_936184 151 bl errata_dsu_936184_wa 152#endif 153 154 ret x19 155endfunc neoverse_n1_reset_func 156 157 /* --------------------------------------------- 158 * HW will do the cache maintenance while powering down 159 * --------------------------------------------- 160 */ 161func neoverse_n1_core_pwr_dwn 162 /* --------------------------------------------- 163 * Enable CPU power down bit in power control register 164 * --------------------------------------------- 165 */ 166 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 167 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 168 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 169 isb 170 ret 171endfunc neoverse_n1_core_pwr_dwn 172 173#if REPORT_ERRATA 174/* 175 * Errata printing function for Neoverse N1. Must follow AAPCS. 176 */ 177func neoverse_n1_errata_report 178 stp x8, x30, [sp, #-16]! 179 180 bl cpu_get_rev_var 181 mov x8, x0 182 183 /* 184 * Report all errata. The revision-variant information is passed to 185 * checking functions of each errata. 186 */ 187 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 188 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 189 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 190 191 ldp x8, x30, [sp], #16 192 ret 193endfunc neoverse_n1_errata_report 194#endif 195 196 /* --------------------------------------------- 197 * This function provides neoverse_n1 specific 198 * register information for crash reporting. 199 * It needs to return with x6 pointing to 200 * a list of register names in ascii and 201 * x8 - x15 having values of registers to be 202 * reported. 203 * --------------------------------------------- 204 */ 205.section .rodata.neoverse_n1_regs, "aS" 206neoverse_n1_regs: /* The ascii list of register names to be reported */ 207 .asciz "cpuectlr_el1", "" 208 209func neoverse_n1_cpu_reg_dump 210 adr x6, neoverse_n1_regs 211 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 212 ret 213endfunc neoverse_n1_cpu_reg_dump 214 215declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 216 neoverse_n1_reset_func, \ 217 neoverse_n1_core_pwr_dwn 218