1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* -------------------------------------------------- 14 * Errata Workaround for Neoverse N1 Errata 15 * This applies to revision r0p0 and r1p0 of Neoverse N1. 16 * Inputs: 17 * x0: variant[4:7] and revision[0:3] of current cpu. 18 * Shall clobber: x0-x17 19 * -------------------------------------------------- 20 */ 21func errata_n1_1043202_wa 22 /* Compare x0 against revision r1p0 */ 23 mov x17, x30 24 bl check_errata_1043202 25 cbz x0, 1f 26 27 /* Apply instruction patching sequence */ 28 ldr x0, =0x0 29 msr CPUPSELR_EL3, x0 30 ldr x0, =0xF3BF8F2F 31 msr CPUPOR_EL3, x0 32 ldr x0, =0xFFFFFFFF 33 msr CPUPMR_EL3, x0 34 ldr x0, =0x800200071 35 msr CPUPCR_EL3, x0 36 isb 371: 38 ret x17 39endfunc errata_n1_1043202_wa 40 41func check_errata_1043202 42 /* Applies to r0p0 and r1p0 */ 43 mov x1, #0x10 44 b cpu_rev_var_ls 45endfunc check_errata_1043202 46 47func neoverse_n1_reset_func 48 mov x19, x30 49 50 /* Disables speculative loads */ 51 msr SSBS, xzr 52 53 bl cpu_get_rev_var 54 mov x18, x0 55 56#if ERRATA_N1_1043202 57 mov x0, x18 58 bl errata_n1_1043202_wa 59#endif 60 61#if ENABLE_AMU 62 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 63 mrs x0, actlr_el3 64 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 65 msr actlr_el3, x0 66 isb 67 68 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 69 mrs x0, actlr_el2 70 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 71 msr actlr_el2, x0 72 isb 73 74 /* Enable group0 counters */ 75 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 76 msr CPUAMCNTENSET_EL0, x0 77 isb 78#endif 79 ret x19 80endfunc neoverse_n1_reset_func 81 82 /* --------------------------------------------- 83 * HW will do the cache maintenance while powering down 84 * --------------------------------------------- 85 */ 86func neoverse_n1_core_pwr_dwn 87 /* --------------------------------------------- 88 * Enable CPU power down bit in power control register 89 * --------------------------------------------- 90 */ 91 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 92 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 93 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 94 isb 95 ret 96endfunc neoverse_n1_core_pwr_dwn 97 98#if REPORT_ERRATA 99/* 100 * Errata printing function for Neoverse N1. Must follow AAPCS. 101 */ 102func neoverse_n1_errata_report 103 stp x8, x30, [sp, #-16]! 104 105 bl cpu_get_rev_var 106 mov x8, x0 107 108 /* 109 * Report all errata. The revision-variant information is passed to 110 * checking functions of each errata. 111 */ 112 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 113 114 ldp x8, x30, [sp], #16 115 ret 116endfunc neoverse_n1_errata_report 117#endif 118 119 /* --------------------------------------------- 120 * This function provides neoverse_n1 specific 121 * register information for crash reporting. 122 * It needs to return with x6 pointing to 123 * a list of register names in ascii and 124 * x8 - x15 having values of registers to be 125 * reported. 126 * --------------------------------------------- 127 */ 128.section .rodata.neoverse_n1_regs, "aS" 129neoverse_n1_regs: /* The ascii list of register names to be reported */ 130 .asciz "cpuectlr_el1", "" 131 132func neoverse_n1_cpu_reg_dump 133 adr x6, neoverse_n1_regs 134 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 135 ret 136endfunc neoverse_n1_cpu_reg_dump 137 138declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 139 neoverse_n1_reset_func, \ 140 neoverse_n1_core_pwr_dwn 141