1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23/* -------------------------------------------------- 24 * Errata Workaround for Neoverse N1 Erratum 1043202. 25 * This applies to revision r0p0 and r1p0 of Neoverse N1. 26 * Inputs: 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_n1_1043202_wa 32 /* Compare x0 against revision r1p0 */ 33 mov x17, x30 34 bl check_errata_1043202 35 cbz x0, 1f 36 37 /* Apply instruction patching sequence */ 38 ldr x0, =0x0 39 msr CPUPSELR_EL3, x0 40 ldr x0, =0xF3BF8F2F 41 msr CPUPOR_EL3, x0 42 ldr x0, =0xFFFFFFFF 43 msr CPUPMR_EL3, x0 44 ldr x0, =0x800200071 45 msr CPUPCR_EL3, x0 46 isb 471: 48 ret x17 49endfunc errata_n1_1043202_wa 50 51func check_errata_1043202 52 /* Applies to r0p0 and r1p0 */ 53 mov x1, #0x10 54 b cpu_rev_var_ls 55endfunc check_errata_1043202 56 57/* -------------------------------------------------- 58 * Disable speculative loads if Neoverse N1 supports 59 * SSBS. 60 * 61 * Shall clobber: x0. 62 * -------------------------------------------------- 63 */ 64func neoverse_n1_disable_speculative_loads 65 /* Check if the PE implements SSBS */ 66 mrs x0, id_aa64pfr1_el1 67 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 68 b.eq 1f 69 70 /* Disable speculative loads */ 71 msr SSBS, xzr 72 isb 73 741: 75 ret 76endfunc neoverse_n1_disable_speculative_loads 77 78/* -------------------------------------------------- 79 * Errata Workaround for Neoverse N1 Errata #1073348 80 * This applies to revision r0p0 and r1p0 of Neoverse N1. 81 * Inputs: 82 * x0: variant[4:7] and revision[0:3] of current cpu. 83 * Shall clobber: x0-x17 84 * -------------------------------------------------- 85 */ 86func errata_n1_1073348_wa 87 /* Compare x0 against revision r1p0 */ 88 mov x17, x30 89 bl check_errata_1073348 90 cbz x0, 1f 91 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 92 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 93 msr NEOVERSE_N1_CPUACTLR_EL1, x1 94 isb 951: 96 ret x17 97endfunc errata_n1_1073348_wa 98 99func check_errata_1073348 100 /* Applies to r0p0 and r1p0 */ 101 mov x1, #0x10 102 b cpu_rev_var_ls 103endfunc check_errata_1073348 104 105/* -------------------------------------------------- 106 * Errata Workaround for Neoverse N1 Erratum 1315703. 107 * This applies to revision <= r3p0 of Neoverse N1. 108 * Inputs: 109 * x0: variant[4:7] and revision[0:3] of current cpu. 110 * Shall clobber: x0-x17 111 * -------------------------------------------------- 112 */ 113func errata_n1_1315703_wa 114 /* Compare x0 against revision r3p1 */ 115 mov x17, x30 116 bl check_errata_1315703 117 cbz x0, 1f 118 119 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 120 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 121 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 122 isb 123 1241: 125 ret x17 126endfunc errata_n1_1315703_wa 127 128func check_errata_1315703 129 /* Applies to everything <= r3p0. */ 130 mov x1, #0x30 131 b cpu_rev_var_ls 132endfunc check_errata_1315703 133 134func neoverse_n1_reset_func 135 mov x19, x30 136 137 bl neoverse_n1_disable_speculative_loads 138 139 /* Forces all cacheable atomic instructions to be near */ 140 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 141 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 142 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 143 isb 144 145 bl cpu_get_rev_var 146 mov x18, x0 147 148#if ERRATA_N1_1043202 149 mov x0, x18 150 bl errata_n1_1043202_wa 151#endif 152 153#if ERRATA_N1_1073348 154 mov x0, x18 155 bl errata_n1_1073348_wa 156#endif 157 158#if ERRATA_N1_1315703 159 mov x0, x18 160 bl errata_n1_1315703_wa 161#endif 162 163#if ENABLE_AMU 164 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 165 mrs x0, actlr_el3 166 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 167 msr actlr_el3, x0 168 isb 169 170 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 171 mrs x0, actlr_el2 172 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 173 msr actlr_el2, x0 174 isb 175 176 /* Enable group0 counters */ 177 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 178 msr CPUAMCNTENSET_EL0, x0 179 isb 180#endif 181 182#if ERRATA_DSU_936184 183 bl errata_dsu_936184_wa 184#endif 185 186 ret x19 187endfunc neoverse_n1_reset_func 188 189 /* --------------------------------------------- 190 * HW will do the cache maintenance while powering down 191 * --------------------------------------------- 192 */ 193func neoverse_n1_core_pwr_dwn 194 /* --------------------------------------------- 195 * Enable CPU power down bit in power control register 196 * --------------------------------------------- 197 */ 198 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 199 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 200 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 201 isb 202 ret 203endfunc neoverse_n1_core_pwr_dwn 204 205#if REPORT_ERRATA 206/* 207 * Errata printing function for Neoverse N1. Must follow AAPCS. 208 */ 209func neoverse_n1_errata_report 210 stp x8, x30, [sp, #-16]! 211 212 bl cpu_get_rev_var 213 mov x8, x0 214 215 /* 216 * Report all errata. The revision-variant information is passed to 217 * checking functions of each errata. 218 */ 219 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 220 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 221 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 222 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 223 224 ldp x8, x30, [sp], #16 225 ret 226endfunc neoverse_n1_errata_report 227#endif 228 229 /* --------------------------------------------- 230 * This function provides neoverse_n1 specific 231 * register information for crash reporting. 232 * It needs to return with x6 pointing to 233 * a list of register names in ascii and 234 * x8 - x15 having values of registers to be 235 * reported. 236 * --------------------------------------------- 237 */ 238.section .rodata.neoverse_n1_regs, "aS" 239neoverse_n1_regs: /* The ascii list of register names to be reported */ 240 .asciz "cpuectlr_el1", "" 241 242func neoverse_n1_cpu_reg_dump 243 adr x6, neoverse_n1_regs 244 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 245 ret 246endfunc neoverse_n1_cpu_reg_dump 247 248declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 249 neoverse_n1_reset_func, \ 250 neoverse_n1_core_pwr_dwn 251