1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23/* -------------------------------------------------- 24 * Errata Workaround for Neoverse N1 Errata 25 * This applies to revision r0p0 and r1p0 of Neoverse N1. 26 * Inputs: 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_n1_1043202_wa 32 /* Compare x0 against revision r1p0 */ 33 mov x17, x30 34 bl check_errata_1043202 35 cbz x0, 1f 36 37 /* Apply instruction patching sequence */ 38 ldr x0, =0x0 39 msr CPUPSELR_EL3, x0 40 ldr x0, =0xF3BF8F2F 41 msr CPUPOR_EL3, x0 42 ldr x0, =0xFFFFFFFF 43 msr CPUPMR_EL3, x0 44 ldr x0, =0x800200071 45 msr CPUPCR_EL3, x0 46 isb 471: 48 ret x17 49endfunc errata_n1_1043202_wa 50 51func check_errata_1043202 52 /* Applies to r0p0 and r1p0 */ 53 mov x1, #0x10 54 b cpu_rev_var_ls 55endfunc check_errata_1043202 56 57/* -------------------------------------------------- 58 * Disable speculative loads if Neoverse N1 supports 59 * SSBS. 60 * 61 * Shall clobber: x0. 62 * -------------------------------------------------- 63 */ 64func neoverse_n1_disable_speculative_loads 65 /* Check if the PE implements SSBS */ 66 mrs x0, id_aa64pfr1_el1 67 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 68 b.eq 1f 69 70 /* Disable speculative loads */ 71 msr SSBS, xzr 72 isb 73 741: 75 ret 76endfunc neoverse_n1_disable_speculative_loads 77 78func neoverse_n1_reset_func 79 mov x19, x30 80 81 bl neoverse_n1_disable_speculative_loads 82 83 /* Forces all cacheable atomic instructions to be near */ 84 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 85 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 86 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 87 isb 88 89 bl cpu_get_rev_var 90 mov x18, x0 91 92#if ERRATA_N1_1043202 93 mov x0, x18 94 bl errata_n1_1043202_wa 95#endif 96 97#if ENABLE_AMU 98 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 99 mrs x0, actlr_el3 100 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 101 msr actlr_el3, x0 102 isb 103 104 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 105 mrs x0, actlr_el2 106 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 107 msr actlr_el2, x0 108 isb 109 110 /* Enable group0 counters */ 111 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 112 msr CPUAMCNTENSET_EL0, x0 113 isb 114#endif 115 ret x19 116endfunc neoverse_n1_reset_func 117 118 /* --------------------------------------------- 119 * HW will do the cache maintenance while powering down 120 * --------------------------------------------- 121 */ 122func neoverse_n1_core_pwr_dwn 123 /* --------------------------------------------- 124 * Enable CPU power down bit in power control register 125 * --------------------------------------------- 126 */ 127 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 128 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 129 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 130 isb 131 ret 132endfunc neoverse_n1_core_pwr_dwn 133 134#if REPORT_ERRATA 135/* 136 * Errata printing function for Neoverse N1. Must follow AAPCS. 137 */ 138func neoverse_n1_errata_report 139 stp x8, x30, [sp, #-16]! 140 141 bl cpu_get_rev_var 142 mov x8, x0 143 144 /* 145 * Report all errata. The revision-variant information is passed to 146 * checking functions of each errata. 147 */ 148 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 149 150 ldp x8, x30, [sp], #16 151 ret 152endfunc neoverse_n1_errata_report 153#endif 154 155 /* --------------------------------------------- 156 * This function provides neoverse_n1 specific 157 * register information for crash reporting. 158 * It needs to return with x6 pointing to 159 * a list of register names in ascii and 160 * x8 - x15 having values of registers to be 161 * reported. 162 * --------------------------------------------- 163 */ 164.section .rodata.neoverse_n1_regs, "aS" 165neoverse_n1_regs: /* The ascii list of register names to be reported */ 166 .asciz "cpuectlr_el1", "" 167 168func neoverse_n1_cpu_reg_dump 169 adr x6, neoverse_n1_regs 170 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 171 ret 172endfunc neoverse_n1_cpu_reg_dump 173 174declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 175 neoverse_n1_reset_func, \ 176 neoverse_n1_core_pwr_dwn 177