1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* -------------------------------------------------- 19 * Errata Workaround for Neoverse N1 Erratum 1043202. 20 * This applies to revision r0p0 and r1p0 of Neoverse N1. 21 * Inputs: 22 * x0: variant[4:7] and revision[0:3] of current cpu. 23 * Shall clobber: x0-x17 24 * -------------------------------------------------- 25 */ 26func errata_n1_1043202_wa 27 /* Compare x0 against revision r1p0 */ 28 mov x17, x30 29 bl check_errata_1043202 30 cbz x0, 1f 31 32 /* Apply instruction patching sequence */ 33 ldr x0, =0x0 34 msr CPUPSELR_EL3, x0 35 ldr x0, =0xF3BF8F2F 36 msr CPUPOR_EL3, x0 37 ldr x0, =0xFFFFFFFF 38 msr CPUPMR_EL3, x0 39 ldr x0, =0x800200071 40 msr CPUPCR_EL3, x0 41 isb 421: 43 ret x17 44endfunc errata_n1_1043202_wa 45 46func check_errata_1043202 47 /* Applies to r0p0 and r1p0 */ 48 mov x1, #0x10 49 b cpu_rev_var_ls 50endfunc check_errata_1043202 51 52/* -------------------------------------------------- 53 * Disable speculative loads if Neoverse N1 supports 54 * SSBS. 55 * 56 * Shall clobber: x0. 57 * -------------------------------------------------- 58 */ 59func neoverse_n1_disable_speculative_loads 60 /* Check if the PE implements SSBS */ 61 mrs x0, id_aa64pfr1_el1 62 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 63 b.eq 1f 64 65 /* Disable speculative loads */ 66 msr SSBS, xzr 67 isb 68 691: 70 ret 71endfunc neoverse_n1_disable_speculative_loads 72 73/* -------------------------------------------------- 74 * Errata Workaround for Neoverse N1 Erratum 1315703. 75 * This applies to revision <= r3p0 of Neoverse N1. 76 * Inputs: 77 * x0: variant[4:7] and revision[0:3] of current cpu. 78 * Shall clobber: x0-x17 79 * -------------------------------------------------- 80 */ 81func errata_n1_1315703_wa 82 /* Compare x0 against revision r3p1 */ 83 mov x17, x30 84 bl check_errata_1315703 85 cbz x0, 1f 86 87 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 88 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 89 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 90 isb 91 921: 93 ret x17 94endfunc errata_n1_1315703_wa 95 96func check_errata_1315703 97 /* Applies to everything <= r3p0. */ 98 mov x1, #0x30 99 b cpu_rev_var_ls 100endfunc check_errata_1315703 101 102func neoverse_n1_reset_func 103 mov x19, x30 104 105 bl neoverse_n1_disable_speculative_loads 106 107 /* Forces all cacheable atomic instructions to be near */ 108 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 109 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 110 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 111 isb 112 113 bl cpu_get_rev_var 114 mov x18, x0 115 116#if ERRATA_N1_1043202 117 mov x0, x18 118 bl errata_n1_1043202_wa 119#endif 120 121#if ERRATA_N1_1315703 122 mov x0, x18 123 bl errata_n1_1315703_wa 124#endif 125 126#if ENABLE_AMU 127 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 128 mrs x0, actlr_el3 129 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 130 msr actlr_el3, x0 131 isb 132 133 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 134 mrs x0, actlr_el2 135 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 136 msr actlr_el2, x0 137 isb 138 139 /* Enable group0 counters */ 140 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 141 msr CPUAMCNTENSET_EL0, x0 142 isb 143#endif 144 ret x19 145endfunc neoverse_n1_reset_func 146 147 /* --------------------------------------------- 148 * HW will do the cache maintenance while powering down 149 * --------------------------------------------- 150 */ 151func neoverse_n1_core_pwr_dwn 152 /* --------------------------------------------- 153 * Enable CPU power down bit in power control register 154 * --------------------------------------------- 155 */ 156 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 157 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 158 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 159 isb 160 ret 161endfunc neoverse_n1_core_pwr_dwn 162 163#if REPORT_ERRATA 164/* 165 * Errata printing function for Neoverse N1. Must follow AAPCS. 166 */ 167func neoverse_n1_errata_report 168 stp x8, x30, [sp, #-16]! 169 170 bl cpu_get_rev_var 171 mov x8, x0 172 173 /* 174 * Report all errata. The revision-variant information is passed to 175 * checking functions of each errata. 176 */ 177 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 178 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 179 180 ldp x8, x30, [sp], #16 181 ret 182endfunc neoverse_n1_errata_report 183#endif 184 185 /* --------------------------------------------- 186 * This function provides neoverse_n1 specific 187 * register information for crash reporting. 188 * It needs to return with x6 pointing to 189 * a list of register names in ascii and 190 * x8 - x15 having values of registers to be 191 * reported. 192 * --------------------------------------------- 193 */ 194.section .rodata.neoverse_n1_regs, "aS" 195neoverse_n1_regs: /* The ascii list of register names to be reported */ 196 .asciz "cpuectlr_el1", "" 197 198func neoverse_n1_cpu_reg_dump 199 adr x6, neoverse_n1_regs 200 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 201 ret 202endfunc neoverse_n1_cpu_reg_dump 203 204declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 205 neoverse_n1_reset_func, \ 206 neoverse_n1_core_pwr_dwn 207