1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23/* -------------------------------------------------- 24 * Errata Workaround for Neoverse N1 Erratum 1043202. 25 * This applies to revision r0p0 and r1p0 of Neoverse N1. 26 * Inputs: 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_n1_1043202_wa 32 /* Compare x0 against revision r1p0 */ 33 mov x17, x30 34 bl check_errata_1043202 35 cbz x0, 1f 36 37 /* Apply instruction patching sequence */ 38 ldr x0, =0x0 39 msr CPUPSELR_EL3, x0 40 ldr x0, =0xF3BF8F2F 41 msr CPUPOR_EL3, x0 42 ldr x0, =0xFFFFFFFF 43 msr CPUPMR_EL3, x0 44 ldr x0, =0x800200071 45 msr CPUPCR_EL3, x0 46 isb 471: 48 ret x17 49endfunc errata_n1_1043202_wa 50 51func check_errata_1043202 52 /* Applies to r0p0 and r1p0 */ 53 mov x1, #0x10 54 b cpu_rev_var_ls 55endfunc check_errata_1043202 56 57/* -------------------------------------------------- 58 * Disable speculative loads if Neoverse N1 supports 59 * SSBS. 60 * 61 * Shall clobber: x0. 62 * -------------------------------------------------- 63 */ 64func neoverse_n1_disable_speculative_loads 65 /* Check if the PE implements SSBS */ 66 mrs x0, id_aa64pfr1_el1 67 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 68 b.eq 1f 69 70 /* Disable speculative loads */ 71 msr SSBS, xzr 72 isb 73 741: 75 ret 76endfunc neoverse_n1_disable_speculative_loads 77 78/* -------------------------------------------------- 79 * Errata Workaround for Neoverse N1 Errata #1073348 80 * This applies to revision r0p0 and r1p0 of Neoverse N1. 81 * Inputs: 82 * x0: variant[4:7] and revision[0:3] of current cpu. 83 * Shall clobber: x0-x17 84 * -------------------------------------------------- 85 */ 86func errata_n1_1073348_wa 87 /* Compare x0 against revision r1p0 */ 88 mov x17, x30 89 bl check_errata_1073348 90 cbz x0, 1f 91 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 92 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 93 msr NEOVERSE_N1_CPUACTLR_EL1, x1 94 isb 951: 96 ret x17 97endfunc errata_n1_1073348_wa 98 99func check_errata_1073348 100 /* Applies to r0p0 and r1p0 */ 101 mov x1, #0x10 102 b cpu_rev_var_ls 103endfunc check_errata_1073348 104 105/* -------------------------------------------------- 106 * Errata Workaround for Neoverse N1 Errata #1130799 107 * This applies to revision <=r2p0 of Neoverse N1. 108 * Inputs: 109 * x0: variant[4:7] and revision[0:3] of current cpu. 110 * Shall clobber: x0-x17 111 * -------------------------------------------------- 112 */ 113func errata_n1_1130799_wa 114 /* Compare x0 against revision r2p0 */ 115 mov x17, x30 116 bl check_errata_1130799 117 cbz x0, 1f 118 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 119 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 120 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 121 isb 1221: 123 ret x17 124endfunc errata_n1_1130799_wa 125 126func check_errata_1130799 127 /* Applies to <=r2p0 */ 128 mov x1, #0x20 129 b cpu_rev_var_ls 130endfunc check_errata_1130799 131 132/* -------------------------------------------------- 133 * Errata Workaround for Neoverse N1 Errata #1165347 134 * This applies to revision <=r2p0 of Neoverse N1. 135 * Inputs: 136 * x0: variant[4:7] and revision[0:3] of current cpu. 137 * Shall clobber: x0-x17 138 * -------------------------------------------------- 139 */ 140func errata_n1_1165347_wa 141 /* Compare x0 against revision r2p0 */ 142 mov x17, x30 143 bl check_errata_1165347 144 cbz x0, 1f 145 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 146 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 147 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 148 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 149 isb 1501: 151 ret x17 152endfunc errata_n1_1165347_wa 153 154func check_errata_1165347 155 /* Applies to <=r2p0 */ 156 mov x1, #0x20 157 b cpu_rev_var_ls 158endfunc check_errata_1165347 159 160/* -------------------------------------------------- 161 * Errata Workaround for Neoverse N1 Errata #1207823 162 * This applies to revision <=r2p0 of Neoverse N1. 163 * Inputs: 164 * x0: variant[4:7] and revision[0:3] of current cpu. 165 * Shall clobber: x0-x17 166 * -------------------------------------------------- 167 */ 168func errata_n1_1207823_wa 169 /* Compare x0 against revision r2p0 */ 170 mov x17, x30 171 bl check_errata_1207823 172 cbz x0, 1f 173 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 174 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 175 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 176 isb 1771: 178 ret x17 179endfunc errata_n1_1207823_wa 180 181func check_errata_1207823 182 /* Applies to <=r2p0 */ 183 mov x1, #0x20 184 b cpu_rev_var_ls 185endfunc check_errata_1207823 186 187/* -------------------------------------------------- 188 * Errata Workaround for Neoverse N1 Errata #1220197 189 * This applies to revision <=r2p0 of Neoverse N1. 190 * Inputs: 191 * x0: variant[4:7] and revision[0:3] of current cpu. 192 * Shall clobber: x0-x17 193 * -------------------------------------------------- 194 */ 195func errata_n1_1220197_wa 196 /* Compare x0 against revision r2p0 */ 197 mov x17, x30 198 bl check_errata_1220197 199 cbz x0, 1f 200 mrs x1, NEOVERSE_N1_CPUECTLR_EL1 201 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK 202 msr NEOVERSE_N1_CPUECTLR_EL1, x1 203 isb 2041: 205 ret x17 206endfunc errata_n1_1220197_wa 207 208func check_errata_1220197 209 /* Applies to <=r2p0 */ 210 mov x1, #0x20 211 b cpu_rev_var_ls 212endfunc check_errata_1220197 213 214/* -------------------------------------------------- 215 * Errata Workaround for Neoverse N1 Errata #1257314 216 * This applies to revision <=r3p0 of Neoverse N1. 217 * Inputs: 218 * x0: variant[4:7] and revision[0:3] of current cpu. 219 * Shall clobber: x0-x17 220 * -------------------------------------------------- 221 */ 222func errata_n1_1257314_wa 223 /* Compare x0 against revision r3p0 */ 224 mov x17, x30 225 bl check_errata_1257314 226 cbz x0, 1f 227 mrs x1, NEOVERSE_N1_CPUACTLR3_EL1 228 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 229 msr NEOVERSE_N1_CPUACTLR3_EL1, x1 230 isb 2311: 232 ret x17 233endfunc errata_n1_1257314_wa 234 235func check_errata_1257314 236 /* Applies to <=r3p0 */ 237 mov x1, #0x30 238 b cpu_rev_var_ls 239endfunc check_errata_1257314 240 241/* -------------------------------------------------- 242 * Errata Workaround for Neoverse N1 Errata #1262606 243 * This applies to revision <=r3p0 of Neoverse N1. 244 * Inputs: 245 * x0: variant[4:7] and revision[0:3] of current cpu. 246 * Shall clobber: x0-x17 247 * -------------------------------------------------- 248 */ 249func errata_n1_1262606_wa 250 /* Compare x0 against revision r3p0 */ 251 mov x17, x30 252 bl check_errata_1262606 253 cbz x0, 1f 254 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 255 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 256 msr NEOVERSE_N1_CPUACTLR_EL1, x1 257 isb 2581: 259 ret x17 260endfunc errata_n1_1262606_wa 261 262func check_errata_1262606 263 /* Applies to <=r3p0 */ 264 mov x1, #0x30 265 b cpu_rev_var_ls 266endfunc check_errata_1262606 267 268/* -------------------------------------------------- 269 * Errata Workaround for Neoverse N1 Erratum 1315703. 270 * This applies to revision <= r3p0 of Neoverse N1. 271 * Inputs: 272 * x0: variant[4:7] and revision[0:3] of current cpu. 273 * Shall clobber: x0-x17 274 * -------------------------------------------------- 275 */ 276func errata_n1_1315703_wa 277 /* Compare x0 against revision r3p1 */ 278 mov x17, x30 279 bl check_errata_1315703 280 cbz x0, 1f 281 282 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 283 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 284 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 285 isb 286 2871: 288 ret x17 289endfunc errata_n1_1315703_wa 290 291func check_errata_1315703 292 /* Applies to everything <= r3p0. */ 293 mov x1, #0x30 294 b cpu_rev_var_ls 295endfunc check_errata_1315703 296 297func neoverse_n1_reset_func 298 mov x19, x30 299 300 bl neoverse_n1_disable_speculative_loads 301 302 /* Forces all cacheable atomic instructions to be near */ 303 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 304 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 305 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 306 isb 307 308 bl cpu_get_rev_var 309 mov x18, x0 310 311#if ERRATA_N1_1043202 312 mov x0, x18 313 bl errata_n1_1043202_wa 314#endif 315 316#if ERRATA_N1_1073348 317 mov x0, x18 318 bl errata_n1_1073348_wa 319#endif 320 321#if ERRATA_N1_1130799 322 mov x0, x18 323 bl errata_n1_1130799_wa 324#endif 325 326#if ERRATA_N1_1165347 327 mov x0, x18 328 bl errata_n1_1165347_wa 329#endif 330 331#if ERRATA_N1_1207823 332 mov x0, x18 333 bl errata_n1_1207823_wa 334#endif 335 336#if ERRATA_N1_1220197 337 mov x0, x18 338 bl errata_n1_1220197_wa 339#endif 340 341#if ERRATA_N1_1257314 342 mov x0, x18 343 bl errata_n1_1257314_wa 344#endif 345 346#if ERRATA_N1_1262606 347 mov x0, x18 348 bl errata_n1_1262606_wa 349#endif 350 351#if ERRATA_N1_1315703 352 mov x0, x18 353 bl errata_n1_1315703_wa 354#endif 355 356#if ENABLE_AMU 357 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 358 mrs x0, actlr_el3 359 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 360 msr actlr_el3, x0 361 isb 362 363 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 364 mrs x0, actlr_el2 365 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 366 msr actlr_el2, x0 367 isb 368 369 /* Enable group0 counters */ 370 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 371 msr CPUAMCNTENSET_EL0, x0 372 isb 373#endif 374 375#if ERRATA_DSU_936184 376 bl errata_dsu_936184_wa 377#endif 378 379 ret x19 380endfunc neoverse_n1_reset_func 381 382 /* --------------------------------------------- 383 * HW will do the cache maintenance while powering down 384 * --------------------------------------------- 385 */ 386func neoverse_n1_core_pwr_dwn 387 /* --------------------------------------------- 388 * Enable CPU power down bit in power control register 389 * --------------------------------------------- 390 */ 391 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 392 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 393 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 394 isb 395 ret 396endfunc neoverse_n1_core_pwr_dwn 397 398#if REPORT_ERRATA 399/* 400 * Errata printing function for Neoverse N1. Must follow AAPCS. 401 */ 402func neoverse_n1_errata_report 403 stp x8, x30, [sp, #-16]! 404 405 bl cpu_get_rev_var 406 mov x8, x0 407 408 /* 409 * Report all errata. The revision-variant information is passed to 410 * checking functions of each errata. 411 */ 412 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 413 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 414 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 415 report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 416 report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 417 report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 418 report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 419 report_errata ERRATA_N1_1262606, neoverse_n1, 1262606 420 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 421 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 422 423 ldp x8, x30, [sp], #16 424 ret 425endfunc neoverse_n1_errata_report 426#endif 427 428 /* --------------------------------------------- 429 * This function provides neoverse_n1 specific 430 * register information for crash reporting. 431 * It needs to return with x6 pointing to 432 * a list of register names in ascii and 433 * x8 - x15 having values of registers to be 434 * reported. 435 * --------------------------------------------- 436 */ 437.section .rodata.neoverse_n1_regs, "aS" 438neoverse_n1_regs: /* The ascii list of register names to be reported */ 439 .asciz "cpuectlr_el1", "" 440 441func neoverse_n1_cpu_reg_dump 442 adr x6, neoverse_n1_regs 443 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 444 ret 445endfunc neoverse_n1_cpu_reg_dump 446 447declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 448 neoverse_n1_reset_func, \ 449 neoverse_n1_core_pwr_dwn 450