1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* 64-bit only core */ 19#if CTX_INCLUDE_AARCH32_REGS == 1 20#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 21#endif 22 23/* -------------------------------------------------- 24 * Errata Workaround for Neoverse N1 Erratum 1043202. 25 * This applies to revision r0p0 and r1p0 of Neoverse N1. 26 * Inputs: 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_n1_1043202_wa 32 /* Compare x0 against revision r1p0 */ 33 mov x17, x30 34 bl check_errata_1043202 35 cbz x0, 1f 36 37 /* Apply instruction patching sequence */ 38 ldr x0, =0x0 39 msr CPUPSELR_EL3, x0 40 ldr x0, =0xF3BF8F2F 41 msr CPUPOR_EL3, x0 42 ldr x0, =0xFFFFFFFF 43 msr CPUPMR_EL3, x0 44 ldr x0, =0x800200071 45 msr CPUPCR_EL3, x0 46 isb 471: 48 ret x17 49endfunc errata_n1_1043202_wa 50 51func check_errata_1043202 52 /* Applies to r0p0 and r1p0 */ 53 mov x1, #0x10 54 b cpu_rev_var_ls 55endfunc check_errata_1043202 56 57/* -------------------------------------------------- 58 * Disable speculative loads if Neoverse N1 supports 59 * SSBS. 60 * 61 * Shall clobber: x0. 62 * -------------------------------------------------- 63 */ 64func neoverse_n1_disable_speculative_loads 65 /* Check if the PE implements SSBS */ 66 mrs x0, id_aa64pfr1_el1 67 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 68 b.eq 1f 69 70 /* Disable speculative loads */ 71 msr SSBS, xzr 72 isb 73 741: 75 ret 76endfunc neoverse_n1_disable_speculative_loads 77 78/* -------------------------------------------------- 79 * Errata Workaround for Neoverse N1 Errata #1073348 80 * This applies to revision r0p0 and r1p0 of Neoverse N1. 81 * Inputs: 82 * x0: variant[4:7] and revision[0:3] of current cpu. 83 * Shall clobber: x0-x17 84 * -------------------------------------------------- 85 */ 86func errata_n1_1073348_wa 87 /* Compare x0 against revision r1p0 */ 88 mov x17, x30 89 bl check_errata_1073348 90 cbz x0, 1f 91 mrs x1, NEOVERSE_N1_CPUACTLR_EL1 92 orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 93 msr NEOVERSE_N1_CPUACTLR_EL1, x1 94 isb 951: 96 ret x17 97endfunc errata_n1_1073348_wa 98 99func check_errata_1073348 100 /* Applies to r0p0 and r1p0 */ 101 mov x1, #0x10 102 b cpu_rev_var_ls 103endfunc check_errata_1073348 104 105/* -------------------------------------------------- 106 * Errata Workaround for Neoverse N1 Errata #1130799 107 * This applies to revision <=r2p0 of Neoverse N1. 108 * Inputs: 109 * x0: variant[4:7] and revision[0:3] of current cpu. 110 * Shall clobber: x0-x17 111 * -------------------------------------------------- 112 */ 113func errata_n1_1130799_wa 114 /* Compare x0 against revision r2p0 */ 115 mov x17, x30 116 bl check_errata_1130799 117 cbz x0, 1f 118 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 119 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 120 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 121 isb 1221: 123 ret x17 124endfunc errata_n1_1130799_wa 125 126func check_errata_1130799 127 /* Applies to <=r2p0 */ 128 mov x1, #0x20 129 b cpu_rev_var_ls 130endfunc check_errata_1130799 131 132/* -------------------------------------------------- 133 * Errata Workaround for Neoverse N1 Errata #1165347 134 * This applies to revision <=r2p0 of Neoverse N1. 135 * Inputs: 136 * x0: variant[4:7] and revision[0:3] of current cpu. 137 * Shall clobber: x0-x17 138 * -------------------------------------------------- 139 */ 140func errata_n1_1165347_wa 141 /* Compare x0 against revision r2p0 */ 142 mov x17, x30 143 bl check_errata_1165347 144 cbz x0, 1f 145 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 146 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 147 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 148 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 149 isb 1501: 151 ret x17 152endfunc errata_n1_1165347_wa 153 154func check_errata_1165347 155 /* Applies to <=r2p0 */ 156 mov x1, #0x20 157 b cpu_rev_var_ls 158endfunc check_errata_1165347 159 160/* -------------------------------------------------- 161 * Errata Workaround for Neoverse N1 Errata #1207823 162 * This applies to revision <=r2p0 of Neoverse N1. 163 * Inputs: 164 * x0: variant[4:7] and revision[0:3] of current cpu. 165 * Shall clobber: x0-x17 166 * -------------------------------------------------- 167 */ 168func errata_n1_1207823_wa 169 /* Compare x0 against revision r2p0 */ 170 mov x17, x30 171 bl check_errata_1207823 172 cbz x0, 1f 173 mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 174 orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 175 msr NEOVERSE_N1_CPUACTLR2_EL1, x1 176 isb 1771: 178 ret x17 179endfunc errata_n1_1207823_wa 180 181func check_errata_1207823 182 /* Applies to <=r2p0 */ 183 mov x1, #0x20 184 b cpu_rev_var_ls 185endfunc check_errata_1207823 186 187/* -------------------------------------------------- 188 * Errata Workaround for Neoverse N1 Errata #1220197 189 * This applies to revision <=r2p0 of Neoverse N1. 190 * Inputs: 191 * x0: variant[4:7] and revision[0:3] of current cpu. 192 * Shall clobber: x0-x17 193 * -------------------------------------------------- 194 */ 195func errata_n1_1220197_wa 196 /* Compare x0 against revision r2p0 */ 197 mov x17, x30 198 bl check_errata_1220197 199 cbz x0, 1f 200 mrs x1, NEOVERSE_N1_CPUECTLR_EL1 201 orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK 202 msr NEOVERSE_N1_CPUECTLR_EL1, x1 203 isb 2041: 205 ret x17 206endfunc errata_n1_1220197_wa 207 208func check_errata_1220197 209 /* Applies to <=r2p0 */ 210 mov x1, #0x20 211 b cpu_rev_var_ls 212endfunc check_errata_1220197 213 214/* -------------------------------------------------- 215 * Errata Workaround for Neoverse N1 Errata #1257314 216 * This applies to revision <=r3p0 of Neoverse N1. 217 * Inputs: 218 * x0: variant[4:7] and revision[0:3] of current cpu. 219 * Shall clobber: x0-x17 220 * -------------------------------------------------- 221 */ 222func errata_n1_1257314_wa 223 /* Compare x0 against revision r3p0 */ 224 mov x17, x30 225 bl check_errata_1257314 226 cbz x0, 1f 227 mrs x1, NEOVERSE_N1_CPUACTLR3_EL1 228 orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 229 msr NEOVERSE_N1_CPUACTLR3_EL1, x1 230 isb 2311: 232 ret x17 233endfunc errata_n1_1257314_wa 234 235func check_errata_1257314 236 /* Applies to <=r3p0 */ 237 mov x1, #0x30 238 b cpu_rev_var_ls 239endfunc check_errata_1257314 240 241/* -------------------------------------------------- 242 * Errata Workaround for Neoverse N1 Erratum 1315703. 243 * This applies to revision <= r3p0 of Neoverse N1. 244 * Inputs: 245 * x0: variant[4:7] and revision[0:3] of current cpu. 246 * Shall clobber: x0-x17 247 * -------------------------------------------------- 248 */ 249func errata_n1_1315703_wa 250 /* Compare x0 against revision r3p1 */ 251 mov x17, x30 252 bl check_errata_1315703 253 cbz x0, 1f 254 255 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 256 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 257 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 258 isb 259 2601: 261 ret x17 262endfunc errata_n1_1315703_wa 263 264func check_errata_1315703 265 /* Applies to everything <= r3p0. */ 266 mov x1, #0x30 267 b cpu_rev_var_ls 268endfunc check_errata_1315703 269 270func neoverse_n1_reset_func 271 mov x19, x30 272 273 bl neoverse_n1_disable_speculative_loads 274 275 /* Forces all cacheable atomic instructions to be near */ 276 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 277 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 278 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 279 isb 280 281 bl cpu_get_rev_var 282 mov x18, x0 283 284#if ERRATA_N1_1043202 285 mov x0, x18 286 bl errata_n1_1043202_wa 287#endif 288 289#if ERRATA_N1_1073348 290 mov x0, x18 291 bl errata_n1_1073348_wa 292#endif 293 294#if ERRATA_N1_1130799 295 mov x0, x18 296 bl errata_n1_1130799_wa 297#endif 298 299#if ERRATA_N1_1165347 300 mov x0, x18 301 bl errata_n1_1165347_wa 302#endif 303 304#if ERRATA_N1_1207823 305 mov x0, x18 306 bl errata_n1_1207823_wa 307#endif 308 309#if ERRATA_N1_1220197 310 mov x0, x18 311 bl errata_n1_1220197_wa 312#endif 313 314#if ERRATA_N1_1257314 315 mov x0, x18 316 bl errata_n1_1257314_wa 317#endif 318 319#if ERRATA_N1_1315703 320 mov x0, x18 321 bl errata_n1_1315703_wa 322#endif 323 324#if ENABLE_AMU 325 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 326 mrs x0, actlr_el3 327 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 328 msr actlr_el3, x0 329 isb 330 331 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 332 mrs x0, actlr_el2 333 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 334 msr actlr_el2, x0 335 isb 336 337 /* Enable group0 counters */ 338 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 339 msr CPUAMCNTENSET_EL0, x0 340 isb 341#endif 342 343#if ERRATA_DSU_936184 344 bl errata_dsu_936184_wa 345#endif 346 347 ret x19 348endfunc neoverse_n1_reset_func 349 350 /* --------------------------------------------- 351 * HW will do the cache maintenance while powering down 352 * --------------------------------------------- 353 */ 354func neoverse_n1_core_pwr_dwn 355 /* --------------------------------------------- 356 * Enable CPU power down bit in power control register 357 * --------------------------------------------- 358 */ 359 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 360 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 361 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 362 isb 363 ret 364endfunc neoverse_n1_core_pwr_dwn 365 366#if REPORT_ERRATA 367/* 368 * Errata printing function for Neoverse N1. Must follow AAPCS. 369 */ 370func neoverse_n1_errata_report 371 stp x8, x30, [sp, #-16]! 372 373 bl cpu_get_rev_var 374 mov x8, x0 375 376 /* 377 * Report all errata. The revision-variant information is passed to 378 * checking functions of each errata. 379 */ 380 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 381 report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 382 report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 383 report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 384 report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 385 report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 386 report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 387 report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 388 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 389 390 ldp x8, x30, [sp], #16 391 ret 392endfunc neoverse_n1_errata_report 393#endif 394 395 /* --------------------------------------------- 396 * This function provides neoverse_n1 specific 397 * register information for crash reporting. 398 * It needs to return with x6 pointing to 399 * a list of register names in ascii and 400 * x8 - x15 having values of registers to be 401 * reported. 402 * --------------------------------------------- 403 */ 404.section .rodata.neoverse_n1_regs, "aS" 405neoverse_n1_regs: /* The ascii list of register names to be reported */ 406 .asciz "cpuectlr_el1", "" 407 408func neoverse_n1_cpu_reg_dump 409 adr x6, neoverse_n1_regs 410 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 411 ret 412endfunc neoverse_n1_cpu_reg_dump 413 414declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 415 neoverse_n1_reset_func, \ 416 neoverse_n1_core_pwr_dwn 417