1*b04ea14bSJohn Tsichritzis/* 2*b04ea14bSJohn Tsichritzis * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*b04ea14bSJohn Tsichritzis * 4*b04ea14bSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5*b04ea14bSJohn Tsichritzis */ 6*b04ea14bSJohn Tsichritzis 7*b04ea14bSJohn Tsichritzis#include <arch.h> 8*b04ea14bSJohn Tsichritzis#include <asm_macros.S> 9*b04ea14bSJohn Tsichritzis#include <cortex_ares.h> 10*b04ea14bSJohn Tsichritzis#include <cpuamu.h> 11*b04ea14bSJohn Tsichritzis#include <cpu_macros.S> 12*b04ea14bSJohn Tsichritzis 13*b04ea14bSJohn Tsichritzis/* -------------------------------------------------- 14*b04ea14bSJohn Tsichritzis * Errata Workaround for Cortex-Ares Errata 15*b04ea14bSJohn Tsichritzis * This applies to revision r0p0 and r1p0 of Cortex-Ares. 16*b04ea14bSJohn Tsichritzis * Inputs: 17*b04ea14bSJohn Tsichritzis * x0: variant[4:7] and revision[0:3] of current cpu. 18*b04ea14bSJohn Tsichritzis * Shall clobber: x0-x17 19*b04ea14bSJohn Tsichritzis * -------------------------------------------------- 20*b04ea14bSJohn Tsichritzis */ 21*b04ea14bSJohn Tsichritzisfunc errata_ares_1043202_wa 22*b04ea14bSJohn Tsichritzis /* Compare x0 against revision r1p0 */ 23*b04ea14bSJohn Tsichritzis mov x17, x30 24*b04ea14bSJohn Tsichritzis bl check_errata_1043202 25*b04ea14bSJohn Tsichritzis cbz x0, 1f 26*b04ea14bSJohn Tsichritzis 27*b04ea14bSJohn Tsichritzis /* Apply instruction patching sequence */ 28*b04ea14bSJohn Tsichritzis ldr x0, =0x0 29*b04ea14bSJohn Tsichritzis msr CPUPSELR_EL3, x0 30*b04ea14bSJohn Tsichritzis ldr x0, =0xF3BF8F2F 31*b04ea14bSJohn Tsichritzis msr CPUPOR_EL3, x0 32*b04ea14bSJohn Tsichritzis ldr x0, =0xFFFFFFFF 33*b04ea14bSJohn Tsichritzis msr CPUPMR_EL3, x0 34*b04ea14bSJohn Tsichritzis ldr x0, =0x800200071 35*b04ea14bSJohn Tsichritzis msr CPUPCR_EL3, x0 36*b04ea14bSJohn Tsichritzis isb 37*b04ea14bSJohn Tsichritzis1: 38*b04ea14bSJohn Tsichritzis ret x17 39*b04ea14bSJohn Tsichritzisendfunc errata_ares_1043202_wa 40*b04ea14bSJohn Tsichritzis 41*b04ea14bSJohn Tsichritzisfunc check_errata_1043202 42*b04ea14bSJohn Tsichritzis /* Applies to r0p0 and r1p0 */ 43*b04ea14bSJohn Tsichritzis mov x1, #0x10 44*b04ea14bSJohn Tsichritzis b cpu_rev_var_ls 45*b04ea14bSJohn Tsichritzisendfunc check_errata_1043202 46*b04ea14bSJohn Tsichritzis 47*b04ea14bSJohn Tsichritzisfunc cortex_ares_reset_func 48*b04ea14bSJohn Tsichritzis mov x19, x30 49*b04ea14bSJohn Tsichritzis bl cpu_get_rev_var 50*b04ea14bSJohn Tsichritzis mov x18, x0 51*b04ea14bSJohn Tsichritzis 52*b04ea14bSJohn Tsichritzis#if ERRATA_ARES_1043202 53*b04ea14bSJohn Tsichritzis mov x0, x18 54*b04ea14bSJohn Tsichritzis bl errata_ares_1043202_wa 55*b04ea14bSJohn Tsichritzis#endif 56*b04ea14bSJohn Tsichritzis 57*b04ea14bSJohn Tsichritzis#if ENABLE_AMU 58*b04ea14bSJohn Tsichritzis /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 59*b04ea14bSJohn Tsichritzis mrs x0, actlr_el3 60*b04ea14bSJohn Tsichritzis orr x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT 61*b04ea14bSJohn Tsichritzis msr actlr_el3, x0 62*b04ea14bSJohn Tsichritzis isb 63*b04ea14bSJohn Tsichritzis 64*b04ea14bSJohn Tsichritzis /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 65*b04ea14bSJohn Tsichritzis mrs x0, actlr_el2 66*b04ea14bSJohn Tsichritzis orr x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT 67*b04ea14bSJohn Tsichritzis msr actlr_el2, x0 68*b04ea14bSJohn Tsichritzis isb 69*b04ea14bSJohn Tsichritzis 70*b04ea14bSJohn Tsichritzis /* Enable group0 counters */ 71*b04ea14bSJohn Tsichritzis mov x0, #CORTEX_ARES_AMU_GROUP0_MASK 72*b04ea14bSJohn Tsichritzis msr CPUAMCNTENSET_EL0, x0 73*b04ea14bSJohn Tsichritzis isb 74*b04ea14bSJohn Tsichritzis#endif 75*b04ea14bSJohn Tsichritzis ret x19 76*b04ea14bSJohn Tsichritzisendfunc cortex_ares_reset_func 77*b04ea14bSJohn Tsichritzis 78*b04ea14bSJohn Tsichritzis /* --------------------------------------------- 79*b04ea14bSJohn Tsichritzis * HW will do the cache maintenance while powering down 80*b04ea14bSJohn Tsichritzis * --------------------------------------------- 81*b04ea14bSJohn Tsichritzis */ 82*b04ea14bSJohn Tsichritzisfunc cortex_ares_core_pwr_dwn 83*b04ea14bSJohn Tsichritzis /* --------------------------------------------- 84*b04ea14bSJohn Tsichritzis * Enable CPU power down bit in power control register 85*b04ea14bSJohn Tsichritzis * --------------------------------------------- 86*b04ea14bSJohn Tsichritzis */ 87*b04ea14bSJohn Tsichritzis mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 88*b04ea14bSJohn Tsichritzis orr x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK 89*b04ea14bSJohn Tsichritzis msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 90*b04ea14bSJohn Tsichritzis isb 91*b04ea14bSJohn Tsichritzis ret 92*b04ea14bSJohn Tsichritzisendfunc cortex_ares_core_pwr_dwn 93*b04ea14bSJohn Tsichritzis 94*b04ea14bSJohn Tsichritzis#if REPORT_ERRATA 95*b04ea14bSJohn Tsichritzis/* 96*b04ea14bSJohn Tsichritzis * Errata printing function for Cortex-Ares. Must follow AAPCS. 97*b04ea14bSJohn Tsichritzis */ 98*b04ea14bSJohn Tsichritzisfunc cortex_ares_errata_report 99*b04ea14bSJohn Tsichritzis stp x8, x30, [sp, #-16]! 100*b04ea14bSJohn Tsichritzis 101*b04ea14bSJohn Tsichritzis bl cpu_get_rev_var 102*b04ea14bSJohn Tsichritzis mov x8, x0 103*b04ea14bSJohn Tsichritzis 104*b04ea14bSJohn Tsichritzis /* 105*b04ea14bSJohn Tsichritzis * Report all errata. The revision-variant information is passed to 106*b04ea14bSJohn Tsichritzis * checking functions of each errata. 107*b04ea14bSJohn Tsichritzis */ 108*b04ea14bSJohn Tsichritzis report_errata ERRATA_ARES_1043202, cortex_ares, 1043202 109*b04ea14bSJohn Tsichritzis 110*b04ea14bSJohn Tsichritzis ldp x8, x30, [sp], #16 111*b04ea14bSJohn Tsichritzis ret 112*b04ea14bSJohn Tsichritzisendfunc cortex_ares_errata_report 113*b04ea14bSJohn Tsichritzis#endif 114*b04ea14bSJohn Tsichritzis 115*b04ea14bSJohn Tsichritzis /* --------------------------------------------- 116*b04ea14bSJohn Tsichritzis * This function provides cortex_ares specific 117*b04ea14bSJohn Tsichritzis * register information for crash reporting. 118*b04ea14bSJohn Tsichritzis * It needs to return with x6 pointing to 119*b04ea14bSJohn Tsichritzis * a list of register names in ascii and 120*b04ea14bSJohn Tsichritzis * x8 - x15 having values of registers to be 121*b04ea14bSJohn Tsichritzis * reported. 122*b04ea14bSJohn Tsichritzis * --------------------------------------------- 123*b04ea14bSJohn Tsichritzis */ 124*b04ea14bSJohn Tsichritzis.section .rodata.cortex_ares_regs, "aS" 125*b04ea14bSJohn Tsichritziscortex_ares_regs: /* The ascii list of register names to be reported */ 126*b04ea14bSJohn Tsichritzis .asciz "cpuectlr_el1", "" 127*b04ea14bSJohn Tsichritzis 128*b04ea14bSJohn Tsichritzisfunc cortex_ares_cpu_reg_dump 129*b04ea14bSJohn Tsichritzis adr x6, cortex_ares_regs 130*b04ea14bSJohn Tsichritzis mrs x8, CORTEX_ARES_CPUECTLR_EL1 131*b04ea14bSJohn Tsichritzis ret 132*b04ea14bSJohn Tsichritzisendfunc cortex_ares_cpu_reg_dump 133*b04ea14bSJohn Tsichritzis 134*b04ea14bSJohn Tsichritzisdeclare_cpu_ops cortex_ares, CORTEX_ARES_MIDR, \ 135*b04ea14bSJohn Tsichritzis cortex_ares_reset_func, \ 136*b04ea14bSJohn Tsichritzis cortex_ares_core_pwr_dwn 137