1/* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <neoverse_e1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19func neoverse_e1_cpu_pwr_dwn 20 mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 21 orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 22 msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0 23 isb 24 ret 25endfunc neoverse_e1_cpu_pwr_dwn 26 27#if REPORT_ERRATA 28/* 29 * Errata printing function for Neoverse N1. Must follow AAPCS. 30 */ 31func neoverse_e1_errata_report 32 ret 33endfunc neoverse_e1_errata_report 34#endif 35 36 37.section .rodata.neoverse_e1_regs, "aS" 38neoverse_e1_regs: /* The ascii list of register names to be reported */ 39 .asciz "cpuectlr_el1", "" 40 41func neoverse_e1_cpu_reg_dump 42 adr x6, neoverse_e1_regs 43 mrs x8, NEOVERSE_E1_ECTLR_EL1 44 ret 45endfunc neoverse_e1_cpu_reg_dump 46 47declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ 48 CPU_NO_RESET_FUNC, \ 49 neoverse_e1_cpu_pwr_dwn 50