1fd4bb0adSJohn Tsichritzis/* 211088e39SJohn Tsichritzis * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3fd4bb0adSJohn Tsichritzis * 4fd4bb0adSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5fd4bb0adSJohn Tsichritzis */ 6fd4bb0adSJohn Tsichritzis#include <arch.h> 7fd4bb0adSJohn Tsichritzis#include <asm_macros.S> 8fd4bb0adSJohn Tsichritzis#include <common/bl_common.h> 9fd4bb0adSJohn Tsichritzis#include <common/debug.h> 1011088e39SJohn Tsichritzis#include <neoverse_e1.h> 11fd4bb0adSJohn Tsichritzis#include <cpu_macros.S> 12fd4bb0adSJohn Tsichritzis#include <plat_macros.S> 13fd4bb0adSJohn Tsichritzis 14076b5f02SJohn Tsichritzis/* Hardware handled coherency */ 15076b5f02SJohn Tsichritzis#if HW_ASSISTED_COHERENCY == 0 16076b5f02SJohn Tsichritzis#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17076b5f02SJohn Tsichritzis#endif 18076b5f02SJohn Tsichritzis 19629d04f5SJohn Tsichritzis/* 64-bit only core */ 20629d04f5SJohn Tsichritzis#if CTX_INCLUDE_AARCH32_REGS == 1 21629d04f5SJohn Tsichritzis#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22629d04f5SJohn Tsichritzis#endif 23629d04f5SJohn Tsichritzis 24*bb2f077aSLouis Mayencourt /* ------------------------------------------------- 25*bb2f077aSLouis Mayencourt * The CPU Ops reset function for Neoverse-E1. 26*bb2f077aSLouis Mayencourt * Shall clobber: x0-x19 27*bb2f077aSLouis Mayencourt * ------------------------------------------------- 28*bb2f077aSLouis Mayencourt */ 29*bb2f077aSLouis Mayencourtfunc neoverse_e1_reset_func 30*bb2f077aSLouis Mayencourt mov x19, x30 31*bb2f077aSLouis Mayencourt 32*bb2f077aSLouis Mayencourt#if ERRATA_DSU_936184 33*bb2f077aSLouis Mayencourt bl errata_dsu_936184_wa 34*bb2f077aSLouis Mayencourt#endif 35*bb2f077aSLouis Mayencourt 36*bb2f077aSLouis Mayencourt ret x19 37*bb2f077aSLouis Mayencourtendfunc neoverse_e1_reset_func 38*bb2f077aSLouis Mayencourt 3911088e39SJohn Tsichritzisfunc neoverse_e1_cpu_pwr_dwn 4011088e39SJohn Tsichritzis mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 4111088e39SJohn Tsichritzis orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 4211088e39SJohn Tsichritzis msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0 43fd4bb0adSJohn Tsichritzis isb 44fd4bb0adSJohn Tsichritzis ret 4511088e39SJohn Tsichritzisendfunc neoverse_e1_cpu_pwr_dwn 46fd4bb0adSJohn Tsichritzis 47fd4bb0adSJohn Tsichritzis#if REPORT_ERRATA 48fd4bb0adSJohn Tsichritzis/* 4911088e39SJohn Tsichritzis * Errata printing function for Neoverse N1. Must follow AAPCS. 50fd4bb0adSJohn Tsichritzis */ 5111088e39SJohn Tsichritzisfunc neoverse_e1_errata_report 52*bb2f077aSLouis Mayencourt stp x8, x30, [sp, #-16]! 53*bb2f077aSLouis Mayencourt 54*bb2f077aSLouis Mayencourt bl cpu_get_rev_var 55*bb2f077aSLouis Mayencourt mov x8, x0 56*bb2f077aSLouis Mayencourt 57*bb2f077aSLouis Mayencourt /* 58*bb2f077aSLouis Mayencourt * Report all errata. The revision-variant information is passed to 59*bb2f077aSLouis Mayencourt * checking functions of each errata. 60*bb2f077aSLouis Mayencourt */ 61*bb2f077aSLouis Mayencourt report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184 62*bb2f077aSLouis Mayencourt 63*bb2f077aSLouis Mayencourt ldp x8, x30, [sp], #16 64fd4bb0adSJohn Tsichritzis ret 6511088e39SJohn Tsichritzisendfunc neoverse_e1_errata_report 66fd4bb0adSJohn Tsichritzis#endif 67fd4bb0adSJohn Tsichritzis 68fd4bb0adSJohn Tsichritzis 6911088e39SJohn Tsichritzis.section .rodata.neoverse_e1_regs, "aS" 7011088e39SJohn Tsichritzisneoverse_e1_regs: /* The ascii list of register names to be reported */ 71fd4bb0adSJohn Tsichritzis .asciz "cpuectlr_el1", "" 72fd4bb0adSJohn Tsichritzis 7311088e39SJohn Tsichritzisfunc neoverse_e1_cpu_reg_dump 7411088e39SJohn Tsichritzis adr x6, neoverse_e1_regs 7511088e39SJohn Tsichritzis mrs x8, NEOVERSE_E1_ECTLR_EL1 76fd4bb0adSJohn Tsichritzis ret 7711088e39SJohn Tsichritzisendfunc neoverse_e1_cpu_reg_dump 78fd4bb0adSJohn Tsichritzis 7911088e39SJohn Tsichritzisdeclare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ 80*bb2f077aSLouis Mayencourt neoverse_e1_reset_func, \ 8111088e39SJohn Tsichritzis neoverse_e1_cpu_pwr_dwn 82