1fd4bb0adSJohn Tsichritzis/* 2*b62673c6SBoyan Karatotev * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3fd4bb0adSJohn Tsichritzis * 4fd4bb0adSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5fd4bb0adSJohn Tsichritzis */ 6fd4bb0adSJohn Tsichritzis#include <arch.h> 7fd4bb0adSJohn Tsichritzis#include <asm_macros.S> 8fd4bb0adSJohn Tsichritzis#include <common/bl_common.h> 9fd4bb0adSJohn Tsichritzis#include <common/debug.h> 10*b62673c6SBoyan Karatotev#include <dsu_macros.S> 1111088e39SJohn Tsichritzis#include <neoverse_e1.h> 12fd4bb0adSJohn Tsichritzis#include <cpu_macros.S> 13fd4bb0adSJohn Tsichritzis#include <plat_macros.S> 14fd4bb0adSJohn Tsichritzis 15076b5f02SJohn Tsichritzis/* Hardware handled coherency */ 16076b5f02SJohn Tsichritzis#if HW_ASSISTED_COHERENCY == 0 17076b5f02SJohn Tsichritzis#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" 18076b5f02SJohn Tsichritzis#endif 19076b5f02SJohn Tsichritzis 20629d04f5SJohn Tsichritzis/* 64-bit only core */ 21629d04f5SJohn Tsichritzis#if CTX_INCLUDE_AARCH32_REGS == 1 22629d04f5SJohn Tsichritzis#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23629d04f5SJohn Tsichritzis#endif 24629d04f5SJohn Tsichritzis 25*b62673c6SBoyan Karatotevworkaround_reset_start neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184 26*b62673c6SBoyan Karatotev errata_dsu_936184_wa_impl 27*b62673c6SBoyan Karatotevworkaround_reset_end neoverse_e1, ERRATUM(936184) 28*b62673c6SBoyan Karatotev 29*b62673c6SBoyan Karatotevcheck_erratum_custom_start neoverse_e1, ERRATUM(936184) 30*b62673c6SBoyan Karatotev branch_if_scu_not_present 2f /* label 1 is used in the macro */ 31*b62673c6SBoyan Karatotev check_errata_dsu_936184_impl 32*b62673c6SBoyan Karatotev 2: 33*b62673c6SBoyan Karatotev ret 34*b62673c6SBoyan Karatotevcheck_erratum_custom_end neoverse_e1, ERRATUM(936184) 35bb2f077aSLouis Mayencourt 36291bb2f4Slaurenw-armcpu_reset_func_start neoverse_e1 37291bb2f4Slaurenw-armcpu_reset_func_end neoverse_e1 38bb2f077aSLouis Mayencourt 3911088e39SJohn Tsichritzisfunc neoverse_e1_cpu_pwr_dwn 4011088e39SJohn Tsichritzis mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 4111088e39SJohn Tsichritzis orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 4211088e39SJohn Tsichritzis msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0 43fd4bb0adSJohn Tsichritzis isb 44fd4bb0adSJohn Tsichritzis ret 4511088e39SJohn Tsichritzisendfunc neoverse_e1_cpu_pwr_dwn 46fd4bb0adSJohn Tsichritzis 4711088e39SJohn Tsichritzis.section .rodata.neoverse_e1_regs, "aS" 4811088e39SJohn Tsichritzisneoverse_e1_regs: /* The ascii list of register names to be reported */ 49fd4bb0adSJohn Tsichritzis .asciz "cpuectlr_el1", "" 50fd4bb0adSJohn Tsichritzis 5111088e39SJohn Tsichritzisfunc neoverse_e1_cpu_reg_dump 5211088e39SJohn Tsichritzis adr x6, neoverse_e1_regs 5311088e39SJohn Tsichritzis mrs x8, NEOVERSE_E1_ECTLR_EL1 54fd4bb0adSJohn Tsichritzis ret 5511088e39SJohn Tsichritzisendfunc neoverse_e1_cpu_reg_dump 56fd4bb0adSJohn Tsichritzis 5711088e39SJohn Tsichritzisdeclare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ 58bb2f077aSLouis Mayencourt neoverse_e1_reset_func, \ 5911088e39SJohn Tsichritzis neoverse_e1_cpu_pwr_dwn 60