1fd4bb0adSJohn Tsichritzis/* 2*291bb2f4Slaurenw-arm * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. 3fd4bb0adSJohn Tsichritzis * 4fd4bb0adSJohn Tsichritzis * SPDX-License-Identifier: BSD-3-Clause 5fd4bb0adSJohn Tsichritzis */ 6fd4bb0adSJohn Tsichritzis#include <arch.h> 7fd4bb0adSJohn Tsichritzis#include <asm_macros.S> 8fd4bb0adSJohn Tsichritzis#include <common/bl_common.h> 9fd4bb0adSJohn Tsichritzis#include <common/debug.h> 1011088e39SJohn Tsichritzis#include <neoverse_e1.h> 11fd4bb0adSJohn Tsichritzis#include <cpu_macros.S> 12fd4bb0adSJohn Tsichritzis#include <plat_macros.S> 13fd4bb0adSJohn Tsichritzis 14076b5f02SJohn Tsichritzis/* Hardware handled coherency */ 15076b5f02SJohn Tsichritzis#if HW_ASSISTED_COHERENCY == 0 16076b5f02SJohn Tsichritzis#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17076b5f02SJohn Tsichritzis#endif 18076b5f02SJohn Tsichritzis 19629d04f5SJohn Tsichritzis/* 64-bit only core */ 20629d04f5SJohn Tsichritzis#if CTX_INCLUDE_AARCH32_REGS == 1 21629d04f5SJohn Tsichritzis#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22629d04f5SJohn Tsichritzis#endif 23629d04f5SJohn Tsichritzis 24*291bb2f4Slaurenw-arm/* 25*291bb2f4Slaurenw-arm * ERRATA_DSU_936184: 26*291bb2f4Slaurenw-arm * The errata is defined in dsu_helpers.S and applies to neoverse_e1. 27*291bb2f4Slaurenw-arm * Henceforth creating symbolic names to the already existing errata 28*291bb2f4Slaurenw-arm * workaround functions to get them registered under the Errata Framework. 29bb2f077aSLouis Mayencourt */ 30*291bb2f4Slaurenw-arm.equ check_erratum_neoverse_e1_936184, check_errata_dsu_936184 31*291bb2f4Slaurenw-arm.equ erratum_neoverse_e1_936184_wa, errata_dsu_936184_wa 32*291bb2f4Slaurenw-armadd_erratum_entry neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET 33bb2f077aSLouis Mayencourt 34*291bb2f4Slaurenw-armcpu_reset_func_start neoverse_e1 35*291bb2f4Slaurenw-armcpu_reset_func_end neoverse_e1 36bb2f077aSLouis Mayencourt 3711088e39SJohn Tsichritzisfunc neoverse_e1_cpu_pwr_dwn 3811088e39SJohn Tsichritzis mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 3911088e39SJohn Tsichritzis orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 4011088e39SJohn Tsichritzis msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0 41fd4bb0adSJohn Tsichritzis isb 42fd4bb0adSJohn Tsichritzis ret 4311088e39SJohn Tsichritzisendfunc neoverse_e1_cpu_pwr_dwn 44fd4bb0adSJohn Tsichritzis 45*291bb2f4Slaurenw-armerrata_report_shim neoverse_e1 46fd4bb0adSJohn Tsichritzis 4711088e39SJohn Tsichritzis.section .rodata.neoverse_e1_regs, "aS" 4811088e39SJohn Tsichritzisneoverse_e1_regs: /* The ascii list of register names to be reported */ 49fd4bb0adSJohn Tsichritzis .asciz "cpuectlr_el1", "" 50fd4bb0adSJohn Tsichritzis 5111088e39SJohn Tsichritzisfunc neoverse_e1_cpu_reg_dump 5211088e39SJohn Tsichritzis adr x6, neoverse_e1_regs 5311088e39SJohn Tsichritzis mrs x8, NEOVERSE_E1_ECTLR_EL1 54fd4bb0adSJohn Tsichritzis ret 5511088e39SJohn Tsichritzisendfunc neoverse_e1_cpu_reg_dump 56fd4bb0adSJohn Tsichritzis 5711088e39SJohn Tsichritzisdeclare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ 58bb2f077aSLouis Mayencourt neoverse_e1_reset_func, \ 5911088e39SJohn Tsichritzis neoverse_e1_cpu_pwr_dwn 60