1*e1fbad0bSRyan Everett/* 2*e1fbad0bSRyan Everett * Copyright (c) 2025, Arm Limited. All rights reserved. 3*e1fbad0bSRyan Everett * 4*e1fbad0bSRyan Everett * SPDX-License-Identifier: BSD-3-Clause 5*e1fbad0bSRyan Everett */ 6*e1fbad0bSRyan Everett 7*e1fbad0bSRyan Everett#include <arch.h> 8*e1fbad0bSRyan Everett#include <asm_macros.S> 9*e1fbad0bSRyan Everett#include <common/bl_common.h> 10*e1fbad0bSRyan Everett#include <lsc25_p_core.h> 11*e1fbad0bSRyan Everett#include <cpu_macros.S> 12*e1fbad0bSRyan Everett#include <plat_macros.S> 13*e1fbad0bSRyan Everett 14*e1fbad0bSRyan Everett/* Hardware handled coherency */ 15*e1fbad0bSRyan Everett#if HW_ASSISTED_COHERENCY == 0 16*e1fbad0bSRyan Everett#error "LSC25 P-core must be compiled with HW_ASSISTED_COHERENCY enabled" 17*e1fbad0bSRyan Everett#endif 18*e1fbad0bSRyan Everett 19*e1fbad0bSRyan Everett/* 64-bit only core */ 20*e1fbad0bSRyan Everett#if CTX_INCLUDE_AARCH32_REGS == 1 21*e1fbad0bSRyan Everett#error "LSC25 P-core supports only AArch64. Compile with " \ 22*e1fbad0bSRyan Everett "CTX_INCLUDE_AARCH32_REGS=0" 23*e1fbad0bSRyan Everett#endif 24*e1fbad0bSRyan Everett 25*e1fbad0bSRyan Everett#if ERRATA_SME_POWER_DOWN == 0 26*e1fbad0bSRyan Everett#error "LSC25 P-core needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27*e1fbad0bSRyan Everett#endif 28*e1fbad0bSRyan Everett 29*e1fbad0bSRyan Everettcpu_reset_prologue lsc25_p_core 30*e1fbad0bSRyan Everett 31*e1fbad0bSRyan Everettcpu_reset_func_start lsc25_p_core 32*e1fbad0bSRyan Everett /* ---------------------------------------------------- 33*e1fbad0bSRyan Everett * Disable speculative loads 34*e1fbad0bSRyan Everett * ---------------------------------------------------- 35*e1fbad0bSRyan Everett */ 36*e1fbad0bSRyan Everett msr SSBS, xzr 37*e1fbad0bSRyan Everett enable_mpmm 38*e1fbad0bSRyan Everettcpu_reset_func_end lsc25_p_core 39*e1fbad0bSRyan Everett 40*e1fbad0bSRyan Everettfunc lsc25_p_core_core_pwr_dwn 41*e1fbad0bSRyan Everett /* --------------------------------------------------- 42*e1fbad0bSRyan Everett * Flip CPU power down bit in power control register. 43*e1fbad0bSRyan Everett * It will be set on powerdown and cleared on wakeup 44*e1fbad0bSRyan Everett * --------------------------------------------------- 45*e1fbad0bSRyan Everett */ 46*e1fbad0bSRyan Everett sysreg_bit_toggle LSC25_P_CORE_IMP_CPUPWRCTLR_EL1, \ 47*e1fbad0bSRyan Everett LSC25_P_CORE_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 48*e1fbad0bSRyan Everett isb 49*e1fbad0bSRyan Everett signal_pabandon_handled 50*e1fbad0bSRyan Everett ret 51*e1fbad0bSRyan Everettendfunc lsc25_p_core_core_pwr_dwn 52*e1fbad0bSRyan Everett 53*e1fbad0bSRyan Everett.section .rodata.lsc25_p_core_regs, "aS" 54*e1fbad0bSRyan Everettlsc25_p_core_regs: /* The ASCII list of register names to be reported */ 55*e1fbad0bSRyan Everett .asciz "cpuectlr_el1", "" 56*e1fbad0bSRyan Everett 57*e1fbad0bSRyan Everettfunc lsc25_p_core_cpu_reg_dump 58*e1fbad0bSRyan Everett adr x6, lsc25_p_core_regs 59*e1fbad0bSRyan Everett mrs x8, LSC25_P_CORE_IMP_CPUECTLR_EL1 60*e1fbad0bSRyan Everett ret 61*e1fbad0bSRyan Everettendfunc lsc25_p_core_cpu_reg_dump 62*e1fbad0bSRyan Everett 63*e1fbad0bSRyan Everettdeclare_cpu_ops lsc25_p_core, LSC25_P_CORE_MIDR, \ 64*e1fbad0bSRyan Everett lsc25_p_core_reset_func, \ 65*e1fbad0bSRyan Everett lsc25_p_core_core_pwr_dwn 66