1*2cdc34c5SArvind Ram Prakash/* 2*2cdc34c5SArvind Ram Prakash * Copyright (c) 2025, Arm Limited. All rights reserved. 3*2cdc34c5SArvind Ram Prakash * 4*2cdc34c5SArvind Ram Prakash * SPDX-License-Identifier: BSD-3-Clause 5*2cdc34c5SArvind Ram Prakash */ 6*2cdc34c5SArvind Ram Prakash 7*2cdc34c5SArvind Ram Prakash#include <arch.h> 8*2cdc34c5SArvind Ram Prakash#include <asm_macros.S> 9*2cdc34c5SArvind Ram Prakash#include <common/bl_common.h> 10*2cdc34c5SArvind Ram Prakash#include <dionysus.h> 11*2cdc34c5SArvind Ram Prakash#include <cpu_macros.S> 12*2cdc34c5SArvind Ram Prakash#include <plat_macros.S> 13*2cdc34c5SArvind Ram Prakash 14*2cdc34c5SArvind Ram Prakash/* Hardware handled coherency */ 15*2cdc34c5SArvind Ram Prakash#if HW_ASSISTED_COHERENCY == 0 16*2cdc34c5SArvind Ram Prakash#error "Dionysus must be compiled with HW_ASSISTED_COHERENCY enabled" 17*2cdc34c5SArvind Ram Prakash#endif 18*2cdc34c5SArvind Ram Prakash 19*2cdc34c5SArvind Ram Prakash/* 64-bit only core */ 20*2cdc34c5SArvind Ram Prakash#if CTX_INCLUDE_AARCH32_REGS == 1 21*2cdc34c5SArvind Ram Prakash#error "Dionysus supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22*2cdc34c5SArvind Ram Prakash#endif 23*2cdc34c5SArvind Ram Prakash 24*2cdc34c5SArvind Ram Prakashcpu_reset_prologue dionysus 25*2cdc34c5SArvind Ram Prakash 26*2cdc34c5SArvind Ram Prakashcpu_reset_func_start dionysus 27*2cdc34c5SArvind Ram Prakash /* ---------------------------------------------------- 28*2cdc34c5SArvind Ram Prakash * Disable speculative loads 29*2cdc34c5SArvind Ram Prakash * ---------------------------------------------------- 30*2cdc34c5SArvind Ram Prakash */ 31*2cdc34c5SArvind Ram Prakash msr SSBS, xzr 32*2cdc34c5SArvind Ram Prakash enable_mpmm 33*2cdc34c5SArvind Ram Prakashcpu_reset_func_end dionysus 34*2cdc34c5SArvind Ram Prakash 35*2cdc34c5SArvind Ram Prakash /* ---------------------------------------------------- 36*2cdc34c5SArvind Ram Prakash * HW will do the cache maintenance while powering down 37*2cdc34c5SArvind Ram Prakash * ---------------------------------------------------- 38*2cdc34c5SArvind Ram Prakash */ 39*2cdc34c5SArvind Ram Prakashfunc dionysus_core_pwr_dwn 40*2cdc34c5SArvind Ram Prakash /* --------------------------------------------------- 41*2cdc34c5SArvind Ram Prakash * Flip CPU power down bit in power control register. 42*2cdc34c5SArvind Ram Prakash * It will be set on powerdown and cleared on wakeup 43*2cdc34c5SArvind Ram Prakash * --------------------------------------------------- 44*2cdc34c5SArvind Ram Prakash */ 45*2cdc34c5SArvind Ram Prakash sysreg_bit_toggle DIONYSUS_CPUPWRCTLR_EL1, \ 46*2cdc34c5SArvind Ram Prakash DIONYSUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 47*2cdc34c5SArvind Ram Prakash isb 48*2cdc34c5SArvind Ram Prakash signal_pabandon_handled 49*2cdc34c5SArvind Ram Prakash ret 50*2cdc34c5SArvind Ram Prakashendfunc dionysus_core_pwr_dwn 51*2cdc34c5SArvind Ram Prakash 52*2cdc34c5SArvind Ram Prakash /* --------------------------------------------- 53*2cdc34c5SArvind Ram Prakash * This function provides Dionysus specific 54*2cdc34c5SArvind Ram Prakash * register information for crash reporting. 55*2cdc34c5SArvind Ram Prakash * It needs to return with x6 pointing to 56*2cdc34c5SArvind Ram Prakash * a list of register names in ascii and 57*2cdc34c5SArvind Ram Prakash * x8 - x15 having values of registers to be 58*2cdc34c5SArvind Ram Prakash * reported. 59*2cdc34c5SArvind Ram Prakash * --------------------------------------------- 60*2cdc34c5SArvind Ram Prakash */ 61*2cdc34c5SArvind Ram Prakash.section .rodata.dionysus_regs, "aS" 62*2cdc34c5SArvind Ram Prakashdionysus_regs: /* The ASCII list of register names to be reported */ 63*2cdc34c5SArvind Ram Prakash .asciz "imp_cpuectlr_el1", "" 64*2cdc34c5SArvind Ram Prakash 65*2cdc34c5SArvind Ram Prakashfunc dionysus_cpu_reg_dump 66*2cdc34c5SArvind Ram Prakash adr x6, dionysus_regs 67*2cdc34c5SArvind Ram Prakash mrs x8, DIONYSUS_IMP_CPUECTLR_EL1 68*2cdc34c5SArvind Ram Prakash ret 69*2cdc34c5SArvind Ram Prakashendfunc dionysus_cpu_reg_dump 70*2cdc34c5SArvind Ram Prakash 71*2cdc34c5SArvind Ram Prakashdeclare_cpu_ops dionysus, DIONYSUS_MIDR, \ 72*2cdc34c5SArvind Ram Prakash dionysus_reset_func, \ 73*2cdc34c5SArvind Ram Prakash dionysus_core_pwr_dwn 74