13a8c55f6SVarun Wadekar/* 2b0301467SVarun Wadekar * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*b2ed9989SVarun Wadekar * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 43a8c55f6SVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 63a8c55f6SVarun Wadekar */ 73a8c55f6SVarun Wadekar 83a8c55f6SVarun Wadekar#include <arch.h> 93a8c55f6SVarun Wadekar#include <asm_macros.S> 103a8c55f6SVarun Wadekar#include <assert_macros.S> 11b0301467SVarun Wadekar#include <context.h> 123a8c55f6SVarun Wadekar#include <denver.h> 133a8c55f6SVarun Wadekar#include <cpu_macros.S> 143a8c55f6SVarun Wadekar#include <plat_macros.S> 153a8c55f6SVarun Wadekar 16b0301467SVarun Wadekar /* ------------------------------------------------- 17b0301467SVarun Wadekar * CVE-2017-5715 mitigation 18b0301467SVarun Wadekar * 19b0301467SVarun Wadekar * Flush the indirect branch predictor and RSB on 20b0301467SVarun Wadekar * entry to EL3 by issuing a newly added instruction 21b0301467SVarun Wadekar * for Denver CPUs. 22b0301467SVarun Wadekar * 23b0301467SVarun Wadekar * To achieve this without performing any branch 24b0301467SVarun Wadekar * instruction, a per-cpu vbar is installed which 25b0301467SVarun Wadekar * executes the workaround and then branches off to 26b0301467SVarun Wadekar * the corresponding vector entry in the main vector 27b0301467SVarun Wadekar * table. 28b0301467SVarun Wadekar * ------------------------------------------------- 29b0301467SVarun Wadekar */ 30b0301467SVarun Wadekarvector_base workaround_bpflush_runtime_exceptions 31b0301467SVarun Wadekar 32b0301467SVarun Wadekar .macro apply_workaround 33b0301467SVarun Wadekar stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 34b0301467SVarun Wadekar 35c5c1af0dSVarun Wadekar /* Disable cycle counter when event counting is prohibited */ 36c5c1af0dSVarun Wadekar mrs x1, pmcr_el0 37c5c1af0dSVarun Wadekar orr x0, x1, #PMCR_EL0_DP_BIT 38c5c1af0dSVarun Wadekar msr pmcr_el0, x0 39c5c1af0dSVarun Wadekar isb 40c5c1af0dSVarun Wadekar 41b0301467SVarun Wadekar /* ------------------------------------------------- 42b0301467SVarun Wadekar * A new write-only system register where a write of 43b0301467SVarun Wadekar * 1 to bit 0 will cause the indirect branch predictor 44b0301467SVarun Wadekar * and RSB to be flushed. 45b0301467SVarun Wadekar * 46b0301467SVarun Wadekar * A write of 0 to bit 0 will be ignored. A write of 47b0301467SVarun Wadekar * 1 to any other bit will cause an MCA. 48b0301467SVarun Wadekar * ------------------------------------------------- 49b0301467SVarun Wadekar */ 50b0301467SVarun Wadekar mov x0, #1 51b0301467SVarun Wadekar msr s3_0_c15_c0_6, x0 52b0301467SVarun Wadekar isb 53b0301467SVarun Wadekar 54b0301467SVarun Wadekar ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 55b0301467SVarun Wadekar .endm 56b0301467SVarun Wadekar 57b0301467SVarun Wadekar /* --------------------------------------------------------------------- 58b0301467SVarun Wadekar * Current EL with SP_EL0 : 0x0 - 0x200 59b0301467SVarun Wadekar * --------------------------------------------------------------------- 60b0301467SVarun Wadekar */ 61b0301467SVarun Wadekarvector_entry workaround_bpflush_sync_exception_sp_el0 62b0301467SVarun Wadekar b sync_exception_sp_el0 63a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_sync_exception_sp_el0 64b0301467SVarun Wadekar 65b0301467SVarun Wadekarvector_entry workaround_bpflush_irq_sp_el0 66b0301467SVarun Wadekar b irq_sp_el0 67a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_irq_sp_el0 68b0301467SVarun Wadekar 69b0301467SVarun Wadekarvector_entry workaround_bpflush_fiq_sp_el0 70b0301467SVarun Wadekar b fiq_sp_el0 71a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_fiq_sp_el0 72b0301467SVarun Wadekar 73b0301467SVarun Wadekarvector_entry workaround_bpflush_serror_sp_el0 74b0301467SVarun Wadekar b serror_sp_el0 75a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_serror_sp_el0 76b0301467SVarun Wadekar 77b0301467SVarun Wadekar /* --------------------------------------------------------------------- 78b0301467SVarun Wadekar * Current EL with SP_ELx: 0x200 - 0x400 79b0301467SVarun Wadekar * --------------------------------------------------------------------- 80b0301467SVarun Wadekar */ 81b0301467SVarun Wadekarvector_entry workaround_bpflush_sync_exception_sp_elx 82b0301467SVarun Wadekar b sync_exception_sp_elx 83a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_sync_exception_sp_elx 84b0301467SVarun Wadekar 85b0301467SVarun Wadekarvector_entry workaround_bpflush_irq_sp_elx 86b0301467SVarun Wadekar b irq_sp_elx 87a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_irq_sp_elx 88b0301467SVarun Wadekar 89b0301467SVarun Wadekarvector_entry workaround_bpflush_fiq_sp_elx 90b0301467SVarun Wadekar b fiq_sp_elx 91a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_fiq_sp_elx 92b0301467SVarun Wadekar 93b0301467SVarun Wadekarvector_entry workaround_bpflush_serror_sp_elx 94b0301467SVarun Wadekar b serror_sp_elx 95a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_serror_sp_elx 96b0301467SVarun Wadekar 97b0301467SVarun Wadekar /* --------------------------------------------------------------------- 98b0301467SVarun Wadekar * Lower EL using AArch64 : 0x400 - 0x600 99b0301467SVarun Wadekar * --------------------------------------------------------------------- 100b0301467SVarun Wadekar */ 101b0301467SVarun Wadekarvector_entry workaround_bpflush_sync_exception_aarch64 102b0301467SVarun Wadekar apply_workaround 103b0301467SVarun Wadekar b sync_exception_aarch64 104a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_sync_exception_aarch64 105b0301467SVarun Wadekar 106b0301467SVarun Wadekarvector_entry workaround_bpflush_irq_aarch64 107b0301467SVarun Wadekar apply_workaround 108b0301467SVarun Wadekar b irq_aarch64 109a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_irq_aarch64 110b0301467SVarun Wadekar 111b0301467SVarun Wadekarvector_entry workaround_bpflush_fiq_aarch64 112b0301467SVarun Wadekar apply_workaround 113b0301467SVarun Wadekar b fiq_aarch64 114a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_fiq_aarch64 115b0301467SVarun Wadekar 116b0301467SVarun Wadekarvector_entry workaround_bpflush_serror_aarch64 117b0301467SVarun Wadekar apply_workaround 118b0301467SVarun Wadekar b serror_aarch64 119a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_serror_aarch64 120b0301467SVarun Wadekar 121b0301467SVarun Wadekar /* --------------------------------------------------------------------- 122b0301467SVarun Wadekar * Lower EL using AArch32 : 0x600 - 0x800 123b0301467SVarun Wadekar * --------------------------------------------------------------------- 124b0301467SVarun Wadekar */ 125b0301467SVarun Wadekarvector_entry workaround_bpflush_sync_exception_aarch32 126b0301467SVarun Wadekar apply_workaround 127b0301467SVarun Wadekar b sync_exception_aarch32 128a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_sync_exception_aarch32 129b0301467SVarun Wadekar 130b0301467SVarun Wadekarvector_entry workaround_bpflush_irq_aarch32 131b0301467SVarun Wadekar apply_workaround 132b0301467SVarun Wadekar b irq_aarch32 133a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_irq_aarch32 134b0301467SVarun Wadekar 135b0301467SVarun Wadekarvector_entry workaround_bpflush_fiq_aarch32 136b0301467SVarun Wadekar apply_workaround 137b0301467SVarun Wadekar b fiq_aarch32 138a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_fiq_aarch32 139b0301467SVarun Wadekar 140b0301467SVarun Wadekarvector_entry workaround_bpflush_serror_aarch32 141b0301467SVarun Wadekar apply_workaround 142b0301467SVarun Wadekar b serror_aarch32 143a9203edaSRoberto Vargasend_vector_entry workaround_bpflush_serror_aarch32 144b0301467SVarun Wadekar 1459f1c5dd1SVarun Wadekar .global denver_disable_dco 1469f1c5dd1SVarun Wadekar 1473a8c55f6SVarun Wadekar /* --------------------------------------------- 1483a8c55f6SVarun Wadekar * Disable debug interfaces 1493a8c55f6SVarun Wadekar * --------------------------------------------- 1503a8c55f6SVarun Wadekar */ 1513a8c55f6SVarun Wadekarfunc denver_disable_ext_debug 1523a8c55f6SVarun Wadekar mov x0, #1 1533a8c55f6SVarun Wadekar msr osdlr_el1, x0 1543a8c55f6SVarun Wadekar isb 1553a8c55f6SVarun Wadekar dsb sy 1563a8c55f6SVarun Wadekar ret 1573a8c55f6SVarun Wadekarendfunc denver_disable_ext_debug 1583a8c55f6SVarun Wadekar 1593a8c55f6SVarun Wadekar /* ---------------------------------------------------- 1603a8c55f6SVarun Wadekar * Enable dynamic code optimizer (DCO) 1613a8c55f6SVarun Wadekar * ---------------------------------------------------- 1623a8c55f6SVarun Wadekar */ 1633a8c55f6SVarun Wadekarfunc denver_enable_dco 1645f902752SVarun Wadekar /* DCO is not supported on PN5 and later */ 1655f902752SVarun Wadekar mrs x1, midr_el1 1665f902752SVarun Wadekar mov_imm x2, DENVER_MIDR_PN4 1675f902752SVarun Wadekar cmp x1, x2 1685f902752SVarun Wadekar b.hi 1f 1695f902752SVarun Wadekar 170e6c0da15SKalyani Chidambaram mov x18, x30 1711593cae4SVarun Wadekar bl plat_my_core_pos 1723a8c55f6SVarun Wadekar mov x1, #1 1733a8c55f6SVarun Wadekar lsl x1, x1, x0 1743a8c55f6SVarun Wadekar msr s3_0_c15_c0_2, x1 175e6c0da15SKalyani Chidambaram mov x30, x18 1765f902752SVarun Wadekar1: ret 1773a8c55f6SVarun Wadekarendfunc denver_enable_dco 1783a8c55f6SVarun Wadekar 1793a8c55f6SVarun Wadekar /* ---------------------------------------------------- 1803a8c55f6SVarun Wadekar * Disable dynamic code optimizer (DCO) 1813a8c55f6SVarun Wadekar * ---------------------------------------------------- 1823a8c55f6SVarun Wadekar */ 1833a8c55f6SVarun Wadekarfunc denver_disable_dco 1845f902752SVarun Wadekar /* DCO is not supported on PN5 and later */ 1855f902752SVarun Wadekar mrs x1, midr_el1 1865f902752SVarun Wadekar mov_imm x2, DENVER_MIDR_PN4 1875f902752SVarun Wadekar cmp x1, x2 1885f902752SVarun Wadekar b.hi 2f 1891593cae4SVarun Wadekar 1903a8c55f6SVarun Wadekar /* turn off background work */ 1915f902752SVarun Wadekar mov x18, x30 1921593cae4SVarun Wadekar bl plat_my_core_pos 1933a8c55f6SVarun Wadekar mov x1, #1 1943a8c55f6SVarun Wadekar lsl x1, x1, x0 1953a8c55f6SVarun Wadekar lsl x2, x1, #16 1963a8c55f6SVarun Wadekar msr s3_0_c15_c0_2, x2 1973a8c55f6SVarun Wadekar isb 1983a8c55f6SVarun Wadekar 1993a8c55f6SVarun Wadekar /* wait till the background work turns off */ 2003a8c55f6SVarun Wadekar1: mrs x2, s3_0_c15_c0_2 2013a8c55f6SVarun Wadekar lsr x2, x2, #32 2023a8c55f6SVarun Wadekar and w2, w2, 0xFFFF 2033a8c55f6SVarun Wadekar and x2, x2, x1 2043a8c55f6SVarun Wadekar cbnz x2, 1b 2053a8c55f6SVarun Wadekar 206e6c0da15SKalyani Chidambaram mov x30, x18 2075f902752SVarun Wadekar2: ret 2083a8c55f6SVarun Wadekarendfunc denver_disable_dco 2093a8c55f6SVarun Wadekar 21083353962SVarun Wadekarfunc check_errata_cve_2017_5715 21183353962SVarun Wadekar mov x0, #ERRATA_MISSING 21283353962SVarun Wadekar#if WORKAROUND_CVE_2017_5715 21383353962SVarun Wadekar /* 21483353962SVarun Wadekar * Check if the CPU supports the special instruction 21583353962SVarun Wadekar * required to flush the indirect branch predictor and 21683353962SVarun Wadekar * RSB. Support for this operation can be determined by 21783353962SVarun Wadekar * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001. 21883353962SVarun Wadekar */ 21983353962SVarun Wadekar mrs x1, id_afr0_el1 22083353962SVarun Wadekar mov x2, #0x10000 22183353962SVarun Wadekar and x1, x1, x2 22283353962SVarun Wadekar cbz x1, 1f 22383353962SVarun Wadekar mov x0, #ERRATA_APPLIES 22483353962SVarun Wadekar1: 22583353962SVarun Wadekar#endif 22683353962SVarun Wadekar ret 22783353962SVarun Wadekarendfunc check_errata_cve_2017_5715 22883353962SVarun Wadekar 2296cf8d65fSVarun Wadekarfunc check_errata_cve_2018_3639 2306cf8d65fSVarun Wadekar#if WORKAROUND_CVE_2018_3639 2316cf8d65fSVarun Wadekar mov x0, #ERRATA_APPLIES 2326cf8d65fSVarun Wadekar#else 2336cf8d65fSVarun Wadekar mov x0, #ERRATA_MISSING 2346cf8d65fSVarun Wadekar#endif 2356cf8d65fSVarun Wadekar ret 2366cf8d65fSVarun Wadekarendfunc check_errata_cve_2018_3639 2376cf8d65fSVarun Wadekar 2383a8c55f6SVarun Wadekar /* ------------------------------------------------- 2393a8c55f6SVarun Wadekar * The CPU Ops reset function for Denver. 2403a8c55f6SVarun Wadekar * ------------------------------------------------- 2413a8c55f6SVarun Wadekar */ 2423a8c55f6SVarun Wadekarfunc denver_reset_func 2433a8c55f6SVarun Wadekar 2443a8c55f6SVarun Wadekar mov x19, x30 2453a8c55f6SVarun Wadekar 246b0301467SVarun Wadekar#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 247b0301467SVarun Wadekar /* 248b0301467SVarun Wadekar * Check if the CPU supports the special instruction 249b0301467SVarun Wadekar * required to flush the indirect branch predictor and 250b0301467SVarun Wadekar * RSB. Support for this operation can be determined by 251b0301467SVarun Wadekar * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001. 252b0301467SVarun Wadekar */ 253b0301467SVarun Wadekar mrs x0, id_afr0_el1 254b0301467SVarun Wadekar mov x1, #0x10000 255b0301467SVarun Wadekar and x0, x0, x1 256b0301467SVarun Wadekar cmp x0, #0 257b0301467SVarun Wadekar adr x1, workaround_bpflush_runtime_exceptions 258b0301467SVarun Wadekar mrs x2, vbar_el3 259b0301467SVarun Wadekar csel x0, x1, x2, ne 260b0301467SVarun Wadekar msr vbar_el3, x0 261b0301467SVarun Wadekar#endif 262b0301467SVarun Wadekar 2636cf8d65fSVarun Wadekar#if WORKAROUND_CVE_2018_3639 2646cf8d65fSVarun Wadekar /* 2656cf8d65fSVarun Wadekar * Denver CPUs with DENVER_MIDR_PN3 or earlier, use different 2666cf8d65fSVarun Wadekar * bits in the ACTLR_EL3 register to disable speculative 2676cf8d65fSVarun Wadekar * store buffer and memory disambiguation. 2686cf8d65fSVarun Wadekar */ 2696cf8d65fSVarun Wadekar mrs x0, midr_el1 2706cf8d65fSVarun Wadekar mov_imm x1, DENVER_MIDR_PN4 2716cf8d65fSVarun Wadekar cmp x0, x1 2726cf8d65fSVarun Wadekar mrs x0, actlr_el3 2736cf8d65fSVarun Wadekar mov x1, #(DENVER_CPU_DIS_MD_EL3 | DENVER_CPU_DIS_SSB_EL3) 2746cf8d65fSVarun Wadekar mov x2, #(DENVER_PN4_CPU_DIS_MD_EL3 | DENVER_PN4_CPU_DIS_SSB_EL3) 2756cf8d65fSVarun Wadekar csel x3, x1, x2, ne 2766cf8d65fSVarun Wadekar orr x0, x0, x3 2776cf8d65fSVarun Wadekar msr actlr_el3, x0 2786cf8d65fSVarun Wadekar isb 2796cf8d65fSVarun Wadekar dsb sy 2806cf8d65fSVarun Wadekar#endif 2816cf8d65fSVarun Wadekar 2823a8c55f6SVarun Wadekar /* ---------------------------------------------------- 283cf3ed0dcSVarun Wadekar * Reset ACTLR.PMSTATE to C1 state 284cf3ed0dcSVarun Wadekar * ---------------------------------------------------- 285cf3ed0dcSVarun Wadekar */ 286cf3ed0dcSVarun Wadekar mrs x0, actlr_el1 287cf3ed0dcSVarun Wadekar bic x0, x0, #DENVER_CPU_PMSTATE_MASK 288cf3ed0dcSVarun Wadekar orr x0, x0, #DENVER_CPU_PMSTATE_C1 289cf3ed0dcSVarun Wadekar msr actlr_el1, x0 290cf3ed0dcSVarun Wadekar 291cf3ed0dcSVarun Wadekar /* ---------------------------------------------------- 2923a8c55f6SVarun Wadekar * Enable dynamic code optimizer (DCO) 2933a8c55f6SVarun Wadekar * ---------------------------------------------------- 2943a8c55f6SVarun Wadekar */ 2953a8c55f6SVarun Wadekar bl denver_enable_dco 2963a8c55f6SVarun Wadekar 2973a8c55f6SVarun Wadekar ret x19 2983a8c55f6SVarun Wadekarendfunc denver_reset_func 2993a8c55f6SVarun Wadekar 3003a8c55f6SVarun Wadekar /* ---------------------------------------------------- 3013a8c55f6SVarun Wadekar * The CPU Ops core power down function for Denver. 3023a8c55f6SVarun Wadekar * ---------------------------------------------------- 3033a8c55f6SVarun Wadekar */ 3043a8c55f6SVarun Wadekarfunc denver_core_pwr_dwn 3053a8c55f6SVarun Wadekar 3063a8c55f6SVarun Wadekar mov x19, x30 3073a8c55f6SVarun Wadekar 3083a8c55f6SVarun Wadekar /* --------------------------------------------- 3093a8c55f6SVarun Wadekar * Force the debug interfaces to be quiescent 3103a8c55f6SVarun Wadekar * --------------------------------------------- 3113a8c55f6SVarun Wadekar */ 3123a8c55f6SVarun Wadekar bl denver_disable_ext_debug 3133a8c55f6SVarun Wadekar 3143a8c55f6SVarun Wadekar ret x19 3153a8c55f6SVarun Wadekarendfunc denver_core_pwr_dwn 3163a8c55f6SVarun Wadekar 3173a8c55f6SVarun Wadekar /* ------------------------------------------------------- 3183a8c55f6SVarun Wadekar * The CPU Ops cluster power down function for Denver. 3193a8c55f6SVarun Wadekar * ------------------------------------------------------- 3203a8c55f6SVarun Wadekar */ 3213a8c55f6SVarun Wadekarfunc denver_cluster_pwr_dwn 3223a8c55f6SVarun Wadekar ret 3233a8c55f6SVarun Wadekarendfunc denver_cluster_pwr_dwn 3243a8c55f6SVarun Wadekar 32583353962SVarun Wadekar#if REPORT_ERRATA 32683353962SVarun Wadekar /* 32783353962SVarun Wadekar * Errata printing function for Denver. Must follow AAPCS. 32883353962SVarun Wadekar */ 32983353962SVarun Wadekarfunc denver_errata_report 33083353962SVarun Wadekar stp x8, x30, [sp, #-16]! 33183353962SVarun Wadekar 33283353962SVarun Wadekar bl cpu_get_rev_var 33383353962SVarun Wadekar mov x8, x0 33483353962SVarun Wadekar 33583353962SVarun Wadekar /* 33683353962SVarun Wadekar * Report all errata. The revision-variant information is passed to 33783353962SVarun Wadekar * checking functions of each errata. 33883353962SVarun Wadekar */ 33983353962SVarun Wadekar report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715 3406cf8d65fSVarun Wadekar report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639 34183353962SVarun Wadekar 34283353962SVarun Wadekar ldp x8, x30, [sp], #16 34383353962SVarun Wadekar ret 34483353962SVarun Wadekarendfunc denver_errata_report 34583353962SVarun Wadekar#endif 34683353962SVarun Wadekar 3473a8c55f6SVarun Wadekar /* --------------------------------------------- 3483a8c55f6SVarun Wadekar * This function provides Denver specific 3493a8c55f6SVarun Wadekar * register information for crash reporting. 3503a8c55f6SVarun Wadekar * It needs to return with x6 pointing to 3513a8c55f6SVarun Wadekar * a list of register names in ascii and 3523a8c55f6SVarun Wadekar * x8 - x15 having values of registers to be 3533a8c55f6SVarun Wadekar * reported. 3543a8c55f6SVarun Wadekar * --------------------------------------------- 3553a8c55f6SVarun Wadekar */ 3563a8c55f6SVarun Wadekar.section .rodata.denver_regs, "aS" 3573a8c55f6SVarun Wadekardenver_regs: /* The ascii list of register names to be reported */ 3583a8c55f6SVarun Wadekar .asciz "actlr_el1", "" 3593a8c55f6SVarun Wadekar 3603a8c55f6SVarun Wadekarfunc denver_cpu_reg_dump 3613a8c55f6SVarun Wadekar adr x6, denver_regs 3623a8c55f6SVarun Wadekar mrs x8, ACTLR_EL1 3633a8c55f6SVarun Wadekar ret 3643a8c55f6SVarun Wadekarendfunc denver_cpu_reg_dump 3653a8c55f6SVarun Wadekar 3669b624a7dSVarun Wadekar/* macro to declare cpu_ops for Denver SKUs */ 3679b624a7dSVarun Wadekar.macro denver_cpu_ops_wa midr 3689b624a7dSVarun Wadekar declare_cpu_ops_wa denver, \midr, \ 369e956e228SVarun Wadekar denver_reset_func, \ 37083353962SVarun Wadekar check_errata_cve_2017_5715, \ 37183353962SVarun Wadekar CPU_NO_EXTRA2_FUNC, \ 372*b2ed9989SVarun Wadekar CPU_NO_EXTRA3_FUNC, \ 373e956e228SVarun Wadekar denver_core_pwr_dwn, \ 374e956e228SVarun Wadekar denver_cluster_pwr_dwn 3759b624a7dSVarun Wadekar.endm 376e956e228SVarun Wadekar 3779b624a7dSVarun Wadekardenver_cpu_ops_wa DENVER_MIDR_PN0 3789b624a7dSVarun Wadekardenver_cpu_ops_wa DENVER_MIDR_PN1 3799b624a7dSVarun Wadekardenver_cpu_ops_wa DENVER_MIDR_PN2 3809b624a7dSVarun Wadekardenver_cpu_ops_wa DENVER_MIDR_PN3 3819b624a7dSVarun Wadekardenver_cpu_ops_wa DENVER_MIDR_PN4 3829b624a7dSVarun Wadekardenver_cpu_ops_wa DENVER_MIDR_PN5 3839b624a7dSVarun Wadekardenver_cpu_ops_wa DENVER_MIDR_PN6 3849b624a7dSVarun Wadekardenver_cpu_ops_wa DENVER_MIDR_PN7 3859b624a7dSVarun Wadekardenver_cpu_ops_wa DENVER_MIDR_PN8 386c6d25c00SHemant Nigamdenver_cpu_ops_wa DENVER_MIDR_PN9 387