13a8c55f6SVarun Wadekar/* 29f1c5dd1SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 33a8c55f6SVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 53a8c55f6SVarun Wadekar */ 63a8c55f6SVarun Wadekar 73a8c55f6SVarun Wadekar#include <arch.h> 83a8c55f6SVarun Wadekar#include <asm_macros.S> 93a8c55f6SVarun Wadekar#include <assert_macros.S> 103a8c55f6SVarun Wadekar#include <denver.h> 113a8c55f6SVarun Wadekar#include <cpu_macros.S> 123a8c55f6SVarun Wadekar#include <plat_macros.S> 133a8c55f6SVarun Wadekar 149f1c5dd1SVarun Wadekar .global denver_disable_dco 159f1c5dd1SVarun Wadekar 163a8c55f6SVarun Wadekar /* --------------------------------------------- 173a8c55f6SVarun Wadekar * Disable debug interfaces 183a8c55f6SVarun Wadekar * --------------------------------------------- 193a8c55f6SVarun Wadekar */ 203a8c55f6SVarun Wadekarfunc denver_disable_ext_debug 213a8c55f6SVarun Wadekar mov x0, #1 223a8c55f6SVarun Wadekar msr osdlr_el1, x0 233a8c55f6SVarun Wadekar isb 243a8c55f6SVarun Wadekar dsb sy 253a8c55f6SVarun Wadekar ret 263a8c55f6SVarun Wadekarendfunc denver_disable_ext_debug 273a8c55f6SVarun Wadekar 283a8c55f6SVarun Wadekar /* ---------------------------------------------------- 293a8c55f6SVarun Wadekar * Enable dynamic code optimizer (DCO) 303a8c55f6SVarun Wadekar * ---------------------------------------------------- 313a8c55f6SVarun Wadekar */ 323a8c55f6SVarun Wadekarfunc denver_enable_dco 333a8c55f6SVarun Wadekar mrs x0, mpidr_el1 343a8c55f6SVarun Wadekar and x0, x0, #0xF 353a8c55f6SVarun Wadekar mov x1, #1 363a8c55f6SVarun Wadekar lsl x1, x1, x0 373a8c55f6SVarun Wadekar msr s3_0_c15_c0_2, x1 383a8c55f6SVarun Wadekar ret 393a8c55f6SVarun Wadekarendfunc denver_enable_dco 403a8c55f6SVarun Wadekar 413a8c55f6SVarun Wadekar /* ---------------------------------------------------- 423a8c55f6SVarun Wadekar * Disable dynamic code optimizer (DCO) 433a8c55f6SVarun Wadekar * ---------------------------------------------------- 443a8c55f6SVarun Wadekar */ 453a8c55f6SVarun Wadekarfunc denver_disable_dco 463a8c55f6SVarun Wadekar 473a8c55f6SVarun Wadekar /* turn off background work */ 483a8c55f6SVarun Wadekar mrs x0, mpidr_el1 493a8c55f6SVarun Wadekar and x0, x0, #0xF 503a8c55f6SVarun Wadekar mov x1, #1 513a8c55f6SVarun Wadekar lsl x1, x1, x0 523a8c55f6SVarun Wadekar lsl x2, x1, #16 533a8c55f6SVarun Wadekar msr s3_0_c15_c0_2, x2 543a8c55f6SVarun Wadekar isb 553a8c55f6SVarun Wadekar 563a8c55f6SVarun Wadekar /* wait till the background work turns off */ 573a8c55f6SVarun Wadekar1: mrs x2, s3_0_c15_c0_2 583a8c55f6SVarun Wadekar lsr x2, x2, #32 593a8c55f6SVarun Wadekar and w2, w2, 0xFFFF 603a8c55f6SVarun Wadekar and x2, x2, x1 613a8c55f6SVarun Wadekar cbnz x2, 1b 623a8c55f6SVarun Wadekar 633a8c55f6SVarun Wadekar ret 643a8c55f6SVarun Wadekarendfunc denver_disable_dco 653a8c55f6SVarun Wadekar 663a8c55f6SVarun Wadekar /* ------------------------------------------------- 673a8c55f6SVarun Wadekar * The CPU Ops reset function for Denver. 683a8c55f6SVarun Wadekar * ------------------------------------------------- 693a8c55f6SVarun Wadekar */ 703a8c55f6SVarun Wadekarfunc denver_reset_func 713a8c55f6SVarun Wadekar 723a8c55f6SVarun Wadekar mov x19, x30 733a8c55f6SVarun Wadekar 743a8c55f6SVarun Wadekar /* ---------------------------------------------------- 753a8c55f6SVarun Wadekar * Enable dynamic code optimizer (DCO) 763a8c55f6SVarun Wadekar * ---------------------------------------------------- 773a8c55f6SVarun Wadekar */ 783a8c55f6SVarun Wadekar bl denver_enable_dco 793a8c55f6SVarun Wadekar 803a8c55f6SVarun Wadekar ret x19 813a8c55f6SVarun Wadekarendfunc denver_reset_func 823a8c55f6SVarun Wadekar 833a8c55f6SVarun Wadekar /* ---------------------------------------------------- 843a8c55f6SVarun Wadekar * The CPU Ops core power down function for Denver. 853a8c55f6SVarun Wadekar * ---------------------------------------------------- 863a8c55f6SVarun Wadekar */ 873a8c55f6SVarun Wadekarfunc denver_core_pwr_dwn 883a8c55f6SVarun Wadekar 893a8c55f6SVarun Wadekar mov x19, x30 903a8c55f6SVarun Wadekar 913a8c55f6SVarun Wadekar /* --------------------------------------------- 923a8c55f6SVarun Wadekar * Force the debug interfaces to be quiescent 933a8c55f6SVarun Wadekar * --------------------------------------------- 943a8c55f6SVarun Wadekar */ 953a8c55f6SVarun Wadekar bl denver_disable_ext_debug 963a8c55f6SVarun Wadekar 973a8c55f6SVarun Wadekar ret x19 983a8c55f6SVarun Wadekarendfunc denver_core_pwr_dwn 993a8c55f6SVarun Wadekar 1003a8c55f6SVarun Wadekar /* ------------------------------------------------------- 1013a8c55f6SVarun Wadekar * The CPU Ops cluster power down function for Denver. 1023a8c55f6SVarun Wadekar * ------------------------------------------------------- 1033a8c55f6SVarun Wadekar */ 1043a8c55f6SVarun Wadekarfunc denver_cluster_pwr_dwn 1053a8c55f6SVarun Wadekar ret 1063a8c55f6SVarun Wadekarendfunc denver_cluster_pwr_dwn 1073a8c55f6SVarun Wadekar 1083a8c55f6SVarun Wadekar /* --------------------------------------------- 1093a8c55f6SVarun Wadekar * This function provides Denver specific 1103a8c55f6SVarun Wadekar * register information for crash reporting. 1113a8c55f6SVarun Wadekar * It needs to return with x6 pointing to 1123a8c55f6SVarun Wadekar * a list of register names in ascii and 1133a8c55f6SVarun Wadekar * x8 - x15 having values of registers to be 1143a8c55f6SVarun Wadekar * reported. 1153a8c55f6SVarun Wadekar * --------------------------------------------- 1163a8c55f6SVarun Wadekar */ 1173a8c55f6SVarun Wadekar.section .rodata.denver_regs, "aS" 1183a8c55f6SVarun Wadekardenver_regs: /* The ascii list of register names to be reported */ 1193a8c55f6SVarun Wadekar .asciz "actlr_el1", "" 1203a8c55f6SVarun Wadekar 1213a8c55f6SVarun Wadekarfunc denver_cpu_reg_dump 1223a8c55f6SVarun Wadekar adr x6, denver_regs 1233a8c55f6SVarun Wadekar mrs x8, ACTLR_EL1 1243a8c55f6SVarun Wadekar ret 1253a8c55f6SVarun Wadekarendfunc denver_cpu_reg_dump 1263a8c55f6SVarun Wadekar 127e956e228SVarun Wadekardeclare_cpu_ops denver, DENVER_MIDR_PN0, \ 128e956e228SVarun Wadekar denver_reset_func, \ 129e956e228SVarun Wadekar denver_core_pwr_dwn, \ 130e956e228SVarun Wadekar denver_cluster_pwr_dwn 131e956e228SVarun Wadekar 132e956e228SVarun Wadekardeclare_cpu_ops denver, DENVER_MIDR_PN1, \ 133e956e228SVarun Wadekar denver_reset_func, \ 134e956e228SVarun Wadekar denver_core_pwr_dwn, \ 135e956e228SVarun Wadekar denver_cluster_pwr_dwn 136e956e228SVarun Wadekar 137e956e228SVarun Wadekardeclare_cpu_ops denver, DENVER_MIDR_PN2, \ 138e956e228SVarun Wadekar denver_reset_func, \ 139e956e228SVarun Wadekar denver_core_pwr_dwn, \ 140e956e228SVarun Wadekar denver_cluster_pwr_dwn 141e956e228SVarun Wadekar 142e956e228SVarun Wadekardeclare_cpu_ops denver, DENVER_MIDR_PN3, \ 143e956e228SVarun Wadekar denver_reset_func, \ 144e956e228SVarun Wadekar denver_core_pwr_dwn, \ 145e956e228SVarun Wadekar denver_cluster_pwr_dwn 146e956e228SVarun Wadekar 147e956e228SVarun Wadekardeclare_cpu_ops denver, DENVER_MIDR_PN4, \ 1485dd9dbb5SJeenu Viswambharan denver_reset_func, \ 1495dd9dbb5SJeenu Viswambharan denver_core_pwr_dwn, \ 1505dd9dbb5SJeenu Viswambharan denver_cluster_pwr_dwn 151