13a8c55f6SVarun Wadekar/* 23a8c55f6SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 33a8c55f6SVarun Wadekar * 43a8c55f6SVarun Wadekar * Redistribution and use in source and binary forms, with or without 53a8c55f6SVarun Wadekar * modification, are permitted provided that the following conditions are met: 63a8c55f6SVarun Wadekar * 73a8c55f6SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 83a8c55f6SVarun Wadekar * list of conditions and the following disclaimer. 93a8c55f6SVarun Wadekar * 103a8c55f6SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 113a8c55f6SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 123a8c55f6SVarun Wadekar * and/or other materials provided with the distribution. 133a8c55f6SVarun Wadekar * 143a8c55f6SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 153a8c55f6SVarun Wadekar * to endorse or promote products derived from this software without specific 163a8c55f6SVarun Wadekar * prior written permission. 173a8c55f6SVarun Wadekar * 183a8c55f6SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 193a8c55f6SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 203a8c55f6SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 213a8c55f6SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 223a8c55f6SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 233a8c55f6SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 243a8c55f6SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 253a8c55f6SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 263a8c55f6SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 273a8c55f6SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 283a8c55f6SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 293a8c55f6SVarun Wadekar */ 303a8c55f6SVarun Wadekar 313a8c55f6SVarun Wadekar#include <arch.h> 323a8c55f6SVarun Wadekar#include <asm_macros.S> 333a8c55f6SVarun Wadekar#include <assert_macros.S> 343a8c55f6SVarun Wadekar#include <denver.h> 353a8c55f6SVarun Wadekar#include <cpu_macros.S> 363a8c55f6SVarun Wadekar#include <plat_macros.S> 373a8c55f6SVarun Wadekar 383a8c55f6SVarun Wadekar /* --------------------------------------------- 393a8c55f6SVarun Wadekar * Disable debug interfaces 403a8c55f6SVarun Wadekar * --------------------------------------------- 413a8c55f6SVarun Wadekar */ 423a8c55f6SVarun Wadekarfunc denver_disable_ext_debug 433a8c55f6SVarun Wadekar mov x0, #1 443a8c55f6SVarun Wadekar msr osdlr_el1, x0 453a8c55f6SVarun Wadekar isb 463a8c55f6SVarun Wadekar dsb sy 473a8c55f6SVarun Wadekar ret 483a8c55f6SVarun Wadekarendfunc denver_disable_ext_debug 493a8c55f6SVarun Wadekar 503a8c55f6SVarun Wadekar /* ---------------------------------------------------- 513a8c55f6SVarun Wadekar * Enable dynamic code optimizer (DCO) 523a8c55f6SVarun Wadekar * ---------------------------------------------------- 533a8c55f6SVarun Wadekar */ 543a8c55f6SVarun Wadekarfunc denver_enable_dco 553a8c55f6SVarun Wadekar mrs x0, mpidr_el1 563a8c55f6SVarun Wadekar and x0, x0, #0xF 573a8c55f6SVarun Wadekar mov x1, #1 583a8c55f6SVarun Wadekar lsl x1, x1, x0 593a8c55f6SVarun Wadekar msr s3_0_c15_c0_2, x1 603a8c55f6SVarun Wadekar isb 613a8c55f6SVarun Wadekar ret 623a8c55f6SVarun Wadekarendfunc denver_enable_dco 633a8c55f6SVarun Wadekar 643a8c55f6SVarun Wadekar /* ---------------------------------------------------- 653a8c55f6SVarun Wadekar * Disable dynamic code optimizer (DCO) 663a8c55f6SVarun Wadekar * ---------------------------------------------------- 673a8c55f6SVarun Wadekar */ 683a8c55f6SVarun Wadekarfunc denver_disable_dco 693a8c55f6SVarun Wadekar 703a8c55f6SVarun Wadekar /* turn off background work */ 713a8c55f6SVarun Wadekar mrs x0, mpidr_el1 723a8c55f6SVarun Wadekar and x0, x0, #0xF 733a8c55f6SVarun Wadekar mov x1, #1 743a8c55f6SVarun Wadekar lsl x1, x1, x0 753a8c55f6SVarun Wadekar lsl x2, x1, #16 763a8c55f6SVarun Wadekar msr s3_0_c15_c0_2, x2 773a8c55f6SVarun Wadekar isb 783a8c55f6SVarun Wadekar 793a8c55f6SVarun Wadekar /* wait till the background work turns off */ 803a8c55f6SVarun Wadekar1: mrs x2, s3_0_c15_c0_2 813a8c55f6SVarun Wadekar lsr x2, x2, #32 823a8c55f6SVarun Wadekar and w2, w2, 0xFFFF 833a8c55f6SVarun Wadekar and x2, x2, x1 843a8c55f6SVarun Wadekar cbnz x2, 1b 853a8c55f6SVarun Wadekar 863a8c55f6SVarun Wadekar ret 873a8c55f6SVarun Wadekarendfunc denver_disable_dco 883a8c55f6SVarun Wadekar 893a8c55f6SVarun Wadekar /* ------------------------------------------------- 903a8c55f6SVarun Wadekar * The CPU Ops reset function for Denver. 913a8c55f6SVarun Wadekar * ------------------------------------------------- 923a8c55f6SVarun Wadekar */ 933a8c55f6SVarun Wadekarfunc denver_reset_func 943a8c55f6SVarun Wadekar 953a8c55f6SVarun Wadekar mov x19, x30 963a8c55f6SVarun Wadekar 973a8c55f6SVarun Wadekar /* ---------------------------------------------------- 983a8c55f6SVarun Wadekar * Enable dynamic code optimizer (DCO) 993a8c55f6SVarun Wadekar * ---------------------------------------------------- 1003a8c55f6SVarun Wadekar */ 1013a8c55f6SVarun Wadekar bl denver_enable_dco 1023a8c55f6SVarun Wadekar 1033a8c55f6SVarun Wadekar ret x19 1043a8c55f6SVarun Wadekarendfunc denver_reset_func 1053a8c55f6SVarun Wadekar 1063a8c55f6SVarun Wadekar /* ---------------------------------------------------- 1073a8c55f6SVarun Wadekar * The CPU Ops core power down function for Denver. 1083a8c55f6SVarun Wadekar * ---------------------------------------------------- 1093a8c55f6SVarun Wadekar */ 1103a8c55f6SVarun Wadekarfunc denver_core_pwr_dwn 1113a8c55f6SVarun Wadekar 1123a8c55f6SVarun Wadekar mov x19, x30 1133a8c55f6SVarun Wadekar 1143a8c55f6SVarun Wadekar /* ---------------------------------------------------- 1153a8c55f6SVarun Wadekar * We enter the 'core power gated with ARM state not 1163a8c55f6SVarun Wadekar * retained' power state during CPU power down. We let 1173a8c55f6SVarun Wadekar * DCO know that we expect to enter this power state 1183a8c55f6SVarun Wadekar * by writing to the ACTLR_EL1 register. 1193a8c55f6SVarun Wadekar * ---------------------------------------------------- 1203a8c55f6SVarun Wadekar */ 1213a8c55f6SVarun Wadekar mov x0, #DENVER_CPU_STATE_POWER_DOWN 1223a8c55f6SVarun Wadekar msr actlr_el1, x0 1233a8c55f6SVarun Wadekar 1243a8c55f6SVarun Wadekar /* --------------------------------------------- 1253a8c55f6SVarun Wadekar * Force DCO to be quiescent 1263a8c55f6SVarun Wadekar * --------------------------------------------- 1273a8c55f6SVarun Wadekar */ 1283a8c55f6SVarun Wadekar bl denver_disable_dco 1293a8c55f6SVarun Wadekar 1303a8c55f6SVarun Wadekar /* --------------------------------------------- 1313a8c55f6SVarun Wadekar * Force the debug interfaces to be quiescent 1323a8c55f6SVarun Wadekar * --------------------------------------------- 1333a8c55f6SVarun Wadekar */ 1343a8c55f6SVarun Wadekar bl denver_disable_ext_debug 1353a8c55f6SVarun Wadekar 1363a8c55f6SVarun Wadekar ret x19 1373a8c55f6SVarun Wadekarendfunc denver_core_pwr_dwn 1383a8c55f6SVarun Wadekar 1393a8c55f6SVarun Wadekar /* ------------------------------------------------------- 1403a8c55f6SVarun Wadekar * The CPU Ops cluster power down function for Denver. 1413a8c55f6SVarun Wadekar * ------------------------------------------------------- 1423a8c55f6SVarun Wadekar */ 1433a8c55f6SVarun Wadekarfunc denver_cluster_pwr_dwn 1443a8c55f6SVarun Wadekar ret 1453a8c55f6SVarun Wadekarendfunc denver_cluster_pwr_dwn 1463a8c55f6SVarun Wadekar 1473a8c55f6SVarun Wadekar /* --------------------------------------------- 1483a8c55f6SVarun Wadekar * This function provides Denver specific 1493a8c55f6SVarun Wadekar * register information for crash reporting. 1503a8c55f6SVarun Wadekar * It needs to return with x6 pointing to 1513a8c55f6SVarun Wadekar * a list of register names in ascii and 1523a8c55f6SVarun Wadekar * x8 - x15 having values of registers to be 1533a8c55f6SVarun Wadekar * reported. 1543a8c55f6SVarun Wadekar * --------------------------------------------- 1553a8c55f6SVarun Wadekar */ 1563a8c55f6SVarun Wadekar.section .rodata.denver_regs, "aS" 1573a8c55f6SVarun Wadekardenver_regs: /* The ascii list of register names to be reported */ 1583a8c55f6SVarun Wadekar .asciz "actlr_el1", "" 1593a8c55f6SVarun Wadekar 1603a8c55f6SVarun Wadekarfunc denver_cpu_reg_dump 1613a8c55f6SVarun Wadekar adr x6, denver_regs 1623a8c55f6SVarun Wadekar mrs x8, ACTLR_EL1 1633a8c55f6SVarun Wadekar ret 1643a8c55f6SVarun Wadekarendfunc denver_cpu_reg_dump 1653a8c55f6SVarun Wadekar 166*5dd9dbb5SJeenu Viswambharandeclare_cpu_ops denver, DENVER_1_0_MIDR, \ 167*5dd9dbb5SJeenu Viswambharan denver_reset_func, \ 168*5dd9dbb5SJeenu Viswambharan denver_core_pwr_dwn, \ 169*5dd9dbb5SJeenu Viswambharan denver_cluster_pwr_dwn 170