1*3a8c55f6SVarun Wadekar/* 2*3a8c55f6SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*3a8c55f6SVarun Wadekar * 4*3a8c55f6SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*3a8c55f6SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*3a8c55f6SVarun Wadekar * 7*3a8c55f6SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*3a8c55f6SVarun Wadekar * list of conditions and the following disclaimer. 9*3a8c55f6SVarun Wadekar * 10*3a8c55f6SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*3a8c55f6SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*3a8c55f6SVarun Wadekar * and/or other materials provided with the distribution. 13*3a8c55f6SVarun Wadekar * 14*3a8c55f6SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*3a8c55f6SVarun Wadekar * to endorse or promote products derived from this software without specific 16*3a8c55f6SVarun Wadekar * prior written permission. 17*3a8c55f6SVarun Wadekar * 18*3a8c55f6SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*3a8c55f6SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*3a8c55f6SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*3a8c55f6SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*3a8c55f6SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*3a8c55f6SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*3a8c55f6SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*3a8c55f6SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*3a8c55f6SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*3a8c55f6SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*3a8c55f6SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*3a8c55f6SVarun Wadekar */ 30*3a8c55f6SVarun Wadekar 31*3a8c55f6SVarun Wadekar#include <arch.h> 32*3a8c55f6SVarun Wadekar#include <asm_macros.S> 33*3a8c55f6SVarun Wadekar#include <assert_macros.S> 34*3a8c55f6SVarun Wadekar#include <denver.h> 35*3a8c55f6SVarun Wadekar#include <cpu_macros.S> 36*3a8c55f6SVarun Wadekar#include <plat_macros.S> 37*3a8c55f6SVarun Wadekar 38*3a8c55f6SVarun Wadekar /* --------------------------------------------- 39*3a8c55f6SVarun Wadekar * Disable debug interfaces 40*3a8c55f6SVarun Wadekar * --------------------------------------------- 41*3a8c55f6SVarun Wadekar */ 42*3a8c55f6SVarun Wadekarfunc denver_disable_ext_debug 43*3a8c55f6SVarun Wadekar mov x0, #1 44*3a8c55f6SVarun Wadekar msr osdlr_el1, x0 45*3a8c55f6SVarun Wadekar isb 46*3a8c55f6SVarun Wadekar dsb sy 47*3a8c55f6SVarun Wadekar ret 48*3a8c55f6SVarun Wadekarendfunc denver_disable_ext_debug 49*3a8c55f6SVarun Wadekar 50*3a8c55f6SVarun Wadekar /* ---------------------------------------------------- 51*3a8c55f6SVarun Wadekar * Enable dynamic code optimizer (DCO) 52*3a8c55f6SVarun Wadekar * ---------------------------------------------------- 53*3a8c55f6SVarun Wadekar */ 54*3a8c55f6SVarun Wadekarfunc denver_enable_dco 55*3a8c55f6SVarun Wadekar mrs x0, mpidr_el1 56*3a8c55f6SVarun Wadekar and x0, x0, #0xF 57*3a8c55f6SVarun Wadekar mov x1, #1 58*3a8c55f6SVarun Wadekar lsl x1, x1, x0 59*3a8c55f6SVarun Wadekar msr s3_0_c15_c0_2, x1 60*3a8c55f6SVarun Wadekar isb 61*3a8c55f6SVarun Wadekar ret 62*3a8c55f6SVarun Wadekarendfunc denver_enable_dco 63*3a8c55f6SVarun Wadekar 64*3a8c55f6SVarun Wadekar /* ---------------------------------------------------- 65*3a8c55f6SVarun Wadekar * Disable dynamic code optimizer (DCO) 66*3a8c55f6SVarun Wadekar * ---------------------------------------------------- 67*3a8c55f6SVarun Wadekar */ 68*3a8c55f6SVarun Wadekarfunc denver_disable_dco 69*3a8c55f6SVarun Wadekar 70*3a8c55f6SVarun Wadekar /* turn off background work */ 71*3a8c55f6SVarun Wadekar mrs x0, mpidr_el1 72*3a8c55f6SVarun Wadekar and x0, x0, #0xF 73*3a8c55f6SVarun Wadekar mov x1, #1 74*3a8c55f6SVarun Wadekar lsl x1, x1, x0 75*3a8c55f6SVarun Wadekar lsl x2, x1, #16 76*3a8c55f6SVarun Wadekar msr s3_0_c15_c0_2, x2 77*3a8c55f6SVarun Wadekar isb 78*3a8c55f6SVarun Wadekar 79*3a8c55f6SVarun Wadekar /* wait till the background work turns off */ 80*3a8c55f6SVarun Wadekar1: mrs x2, s3_0_c15_c0_2 81*3a8c55f6SVarun Wadekar lsr x2, x2, #32 82*3a8c55f6SVarun Wadekar and w2, w2, 0xFFFF 83*3a8c55f6SVarun Wadekar and x2, x2, x1 84*3a8c55f6SVarun Wadekar cbnz x2, 1b 85*3a8c55f6SVarun Wadekar 86*3a8c55f6SVarun Wadekar ret 87*3a8c55f6SVarun Wadekarendfunc denver_disable_dco 88*3a8c55f6SVarun Wadekar 89*3a8c55f6SVarun Wadekar /* ------------------------------------------------- 90*3a8c55f6SVarun Wadekar * The CPU Ops reset function for Denver. 91*3a8c55f6SVarun Wadekar * ------------------------------------------------- 92*3a8c55f6SVarun Wadekar */ 93*3a8c55f6SVarun Wadekarfunc denver_reset_func 94*3a8c55f6SVarun Wadekar 95*3a8c55f6SVarun Wadekar mov x19, x30 96*3a8c55f6SVarun Wadekar 97*3a8c55f6SVarun Wadekar /* ---------------------------------------------------- 98*3a8c55f6SVarun Wadekar * Enable dynamic code optimizer (DCO) 99*3a8c55f6SVarun Wadekar * ---------------------------------------------------- 100*3a8c55f6SVarun Wadekar */ 101*3a8c55f6SVarun Wadekar bl denver_enable_dco 102*3a8c55f6SVarun Wadekar 103*3a8c55f6SVarun Wadekar ret x19 104*3a8c55f6SVarun Wadekarendfunc denver_reset_func 105*3a8c55f6SVarun Wadekar 106*3a8c55f6SVarun Wadekar /* ---------------------------------------------------- 107*3a8c55f6SVarun Wadekar * The CPU Ops core power down function for Denver. 108*3a8c55f6SVarun Wadekar * ---------------------------------------------------- 109*3a8c55f6SVarun Wadekar */ 110*3a8c55f6SVarun Wadekarfunc denver_core_pwr_dwn 111*3a8c55f6SVarun Wadekar 112*3a8c55f6SVarun Wadekar mov x19, x30 113*3a8c55f6SVarun Wadekar 114*3a8c55f6SVarun Wadekar /* ---------------------------------------------------- 115*3a8c55f6SVarun Wadekar * We enter the 'core power gated with ARM state not 116*3a8c55f6SVarun Wadekar * retained' power state during CPU power down. We let 117*3a8c55f6SVarun Wadekar * DCO know that we expect to enter this power state 118*3a8c55f6SVarun Wadekar * by writing to the ACTLR_EL1 register. 119*3a8c55f6SVarun Wadekar * ---------------------------------------------------- 120*3a8c55f6SVarun Wadekar */ 121*3a8c55f6SVarun Wadekar mov x0, #DENVER_CPU_STATE_POWER_DOWN 122*3a8c55f6SVarun Wadekar msr actlr_el1, x0 123*3a8c55f6SVarun Wadekar 124*3a8c55f6SVarun Wadekar /* --------------------------------------------- 125*3a8c55f6SVarun Wadekar * Force DCO to be quiescent 126*3a8c55f6SVarun Wadekar * --------------------------------------------- 127*3a8c55f6SVarun Wadekar */ 128*3a8c55f6SVarun Wadekar bl denver_disable_dco 129*3a8c55f6SVarun Wadekar 130*3a8c55f6SVarun Wadekar /* --------------------------------------------- 131*3a8c55f6SVarun Wadekar * Force the debug interfaces to be quiescent 132*3a8c55f6SVarun Wadekar * --------------------------------------------- 133*3a8c55f6SVarun Wadekar */ 134*3a8c55f6SVarun Wadekar bl denver_disable_ext_debug 135*3a8c55f6SVarun Wadekar 136*3a8c55f6SVarun Wadekar ret x19 137*3a8c55f6SVarun Wadekarendfunc denver_core_pwr_dwn 138*3a8c55f6SVarun Wadekar 139*3a8c55f6SVarun Wadekar /* ------------------------------------------------------- 140*3a8c55f6SVarun Wadekar * The CPU Ops cluster power down function for Denver. 141*3a8c55f6SVarun Wadekar * ------------------------------------------------------- 142*3a8c55f6SVarun Wadekar */ 143*3a8c55f6SVarun Wadekarfunc denver_cluster_pwr_dwn 144*3a8c55f6SVarun Wadekar ret 145*3a8c55f6SVarun Wadekarendfunc denver_cluster_pwr_dwn 146*3a8c55f6SVarun Wadekar 147*3a8c55f6SVarun Wadekar /* --------------------------------------------- 148*3a8c55f6SVarun Wadekar * This function provides Denver specific 149*3a8c55f6SVarun Wadekar * register information for crash reporting. 150*3a8c55f6SVarun Wadekar * It needs to return with x6 pointing to 151*3a8c55f6SVarun Wadekar * a list of register names in ascii and 152*3a8c55f6SVarun Wadekar * x8 - x15 having values of registers to be 153*3a8c55f6SVarun Wadekar * reported. 154*3a8c55f6SVarun Wadekar * --------------------------------------------- 155*3a8c55f6SVarun Wadekar */ 156*3a8c55f6SVarun Wadekar.section .rodata.denver_regs, "aS" 157*3a8c55f6SVarun Wadekardenver_regs: /* The ascii list of register names to be reported */ 158*3a8c55f6SVarun Wadekar .asciz "actlr_el1", "" 159*3a8c55f6SVarun Wadekar 160*3a8c55f6SVarun Wadekarfunc denver_cpu_reg_dump 161*3a8c55f6SVarun Wadekar adr x6, denver_regs 162*3a8c55f6SVarun Wadekar mrs x8, ACTLR_EL1 163*3a8c55f6SVarun Wadekar ret 164*3a8c55f6SVarun Wadekarendfunc denver_cpu_reg_dump 165*3a8c55f6SVarun Wadekar 166*3a8c55f6SVarun Wadekardeclare_cpu_ops denver, DENVER_1_0_MIDR 167