1*a2e702a2SDimitris Papastamos/* 2*a2e702a2SDimitris Papastamos * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*a2e702a2SDimitris Papastamos * 4*a2e702a2SDimitris Papastamos * SPDX-License-Identifier: BSD-3-Clause 5*a2e702a2SDimitris Papastamos */ 6*a2e702a2SDimitris Papastamos 7*a2e702a2SDimitris Papastamos#include <arch.h> 8*a2e702a2SDimitris Papastamos#include <asm_macros.S> 9*a2e702a2SDimitris Papastamos#include <cpuamu.h> 10*a2e702a2SDimitris Papastamos 11*a2e702a2SDimitris Papastamos .globl cpuamu_cnt_read 12*a2e702a2SDimitris Papastamos .globl cpuamu_cnt_write 13*a2e702a2SDimitris Papastamos .globl cpuamu_read_cpuamcntenset_el0 14*a2e702a2SDimitris Papastamos .globl cpuamu_read_cpuamcntenclr_el0 15*a2e702a2SDimitris Papastamos .globl cpuamu_write_cpuamcntenset_el0 16*a2e702a2SDimitris Papastamos .globl cpuamu_write_cpuamcntenclr_el0 17*a2e702a2SDimitris Papastamos 18*a2e702a2SDimitris Papastamos/* 19*a2e702a2SDimitris Papastamos * uint64_t cpuamu_cnt_read(int idx); 20*a2e702a2SDimitris Papastamos * 21*a2e702a2SDimitris Papastamos * Given `idx`, read the corresponding AMU counter 22*a2e702a2SDimitris Papastamos * and return it in `x0`. 23*a2e702a2SDimitris Papastamos */ 24*a2e702a2SDimitris Papastamosfunc cpuamu_cnt_read 25*a2e702a2SDimitris Papastamos adr x1, 1f 26*a2e702a2SDimitris Papastamos lsl x0, x0, #3 27*a2e702a2SDimitris Papastamos add x1, x1, x0 28*a2e702a2SDimitris Papastamos br x1 29*a2e702a2SDimitris Papastamos 30*a2e702a2SDimitris Papastamos1: 31*a2e702a2SDimitris Papastamos mrs x0, CPUAMEVCNTR0_EL0 32*a2e702a2SDimitris Papastamos ret 33*a2e702a2SDimitris Papastamos mrs x0, CPUAMEVCNTR1_EL0 34*a2e702a2SDimitris Papastamos ret 35*a2e702a2SDimitris Papastamos mrs x0, CPUAMEVCNTR2_EL0 36*a2e702a2SDimitris Papastamos ret 37*a2e702a2SDimitris Papastamos mrs x0, CPUAMEVCNTR3_EL0 38*a2e702a2SDimitris Papastamos ret 39*a2e702a2SDimitris Papastamos mrs x0, CPUAMEVCNTR4_EL0 40*a2e702a2SDimitris Papastamos ret 41*a2e702a2SDimitris Papastamosendfunc cpuamu_cnt_read 42*a2e702a2SDimitris Papastamos 43*a2e702a2SDimitris Papastamos/* 44*a2e702a2SDimitris Papastamos * void cpuamu_cnt_write(int idx, uint64_t val); 45*a2e702a2SDimitris Papastamos * 46*a2e702a2SDimitris Papastamos * Given `idx`, write `val` to the corresponding AMU counter. 47*a2e702a2SDimitris Papastamos */ 48*a2e702a2SDimitris Papastamosfunc cpuamu_cnt_write 49*a2e702a2SDimitris Papastamos adr x2, 1f 50*a2e702a2SDimitris Papastamos lsl x0, x0, #3 51*a2e702a2SDimitris Papastamos add x2, x2, x0 52*a2e702a2SDimitris Papastamos br x2 53*a2e702a2SDimitris Papastamos 54*a2e702a2SDimitris Papastamos1: 55*a2e702a2SDimitris Papastamos msr CPUAMEVCNTR0_EL0, x0 56*a2e702a2SDimitris Papastamos ret 57*a2e702a2SDimitris Papastamos msr CPUAMEVCNTR1_EL0, x0 58*a2e702a2SDimitris Papastamos ret 59*a2e702a2SDimitris Papastamos msr CPUAMEVCNTR2_EL0, x0 60*a2e702a2SDimitris Papastamos ret 61*a2e702a2SDimitris Papastamos msr CPUAMEVCNTR3_EL0, x0 62*a2e702a2SDimitris Papastamos ret 63*a2e702a2SDimitris Papastamos msr CPUAMEVCNTR4_EL0, x0 64*a2e702a2SDimitris Papastamos ret 65*a2e702a2SDimitris Papastamosendfunc cpuamu_cnt_write 66*a2e702a2SDimitris Papastamos 67*a2e702a2SDimitris Papastamos/* 68*a2e702a2SDimitris Papastamos * unsigned int cpuamu_read_cpuamcntenset_el0(void); 69*a2e702a2SDimitris Papastamos * 70*a2e702a2SDimitris Papastamos * Read the `CPUAMCNTENSET_EL0` CPU register and return 71*a2e702a2SDimitris Papastamos * it in `x0`. 72*a2e702a2SDimitris Papastamos */ 73*a2e702a2SDimitris Papastamosfunc cpuamu_read_cpuamcntenset_el0 74*a2e702a2SDimitris Papastamos mrs x0, CPUAMCNTENSET_EL0 75*a2e702a2SDimitris Papastamos ret 76*a2e702a2SDimitris Papastamosendfunc cpuamu_read_cpuamcntenset_el0 77*a2e702a2SDimitris Papastamos 78*a2e702a2SDimitris Papastamos/* 79*a2e702a2SDimitris Papastamos * unsigned int cpuamu_read_cpuamcntenclr_el0(void); 80*a2e702a2SDimitris Papastamos * 81*a2e702a2SDimitris Papastamos * Read the `CPUAMCNTENCLR_EL0` CPU register and return 82*a2e702a2SDimitris Papastamos * it in `x0`. 83*a2e702a2SDimitris Papastamos */ 84*a2e702a2SDimitris Papastamosfunc cpuamu_read_cpuamcntenclr_el0 85*a2e702a2SDimitris Papastamos mrs x0, CPUAMCNTENCLR_EL0 86*a2e702a2SDimitris Papastamos ret 87*a2e702a2SDimitris Papastamosendfunc cpuamu_read_cpuamcntenclr_el0 88*a2e702a2SDimitris Papastamos 89*a2e702a2SDimitris Papastamos/* 90*a2e702a2SDimitris Papastamos * void cpuamu_write_cpuamcntenset_el0(unsigned int mask); 91*a2e702a2SDimitris Papastamos * 92*a2e702a2SDimitris Papastamos * Write `mask` to the `CPUAMCNTENSET_EL0` CPU register. 93*a2e702a2SDimitris Papastamos */ 94*a2e702a2SDimitris Papastamosfunc cpuamu_write_cpuamcntenset_el0 95*a2e702a2SDimitris Papastamos msr CPUAMCNTENSET_EL0, x0 96*a2e702a2SDimitris Papastamos ret 97*a2e702a2SDimitris Papastamosendfunc cpuamu_write_cpuamcntenset_el0 98*a2e702a2SDimitris Papastamos 99*a2e702a2SDimitris Papastamos/* 100*a2e702a2SDimitris Papastamos * void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); 101*a2e702a2SDimitris Papastamos * 102*a2e702a2SDimitris Papastamos * Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register. 103*a2e702a2SDimitris Papastamos */ 104*a2e702a2SDimitris Papastamosfunc cpuamu_write_cpuamcntenclr_el0 105*a2e702a2SDimitris Papastamos msr CPUAMCNTENCLR_EL0, x0 106*a2e702a2SDimitris Papastamos ret 107*a2e702a2SDimitris Papastamosendfunc cpuamu_write_cpuamcntenclr_el0 108