1a2e702a2SDimitris Papastamos/* 2a2e702a2SDimitris Papastamos * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3a2e702a2SDimitris Papastamos * 4a2e702a2SDimitris Papastamos * SPDX-License-Identifier: BSD-3-Clause 5a2e702a2SDimitris Papastamos */ 6a2e702a2SDimitris Papastamos 7a2e702a2SDimitris Papastamos#include <arch.h> 8a2e702a2SDimitris Papastamos#include <asm_macros.S> 9a2e702a2SDimitris Papastamos#include <cpuamu.h> 10a2e702a2SDimitris Papastamos 11a2e702a2SDimitris Papastamos .globl cpuamu_cnt_read 12a2e702a2SDimitris Papastamos .globl cpuamu_cnt_write 13a2e702a2SDimitris Papastamos .globl cpuamu_read_cpuamcntenset_el0 14a2e702a2SDimitris Papastamos .globl cpuamu_read_cpuamcntenclr_el0 15a2e702a2SDimitris Papastamos .globl cpuamu_write_cpuamcntenset_el0 16a2e702a2SDimitris Papastamos .globl cpuamu_write_cpuamcntenclr_el0 17a2e702a2SDimitris Papastamos 18a2e702a2SDimitris Papastamos/* 19*40daecc1SAntonio Nino Diaz * uint64_t cpuamu_cnt_read(unsigned int idx); 20a2e702a2SDimitris Papastamos * 21a2e702a2SDimitris Papastamos * Given `idx`, read the corresponding AMU counter 22a2e702a2SDimitris Papastamos * and return it in `x0`. 23a2e702a2SDimitris Papastamos */ 24a2e702a2SDimitris Papastamosfunc cpuamu_cnt_read 25a2e702a2SDimitris Papastamos adr x1, 1f 26a2e702a2SDimitris Papastamos lsl x0, x0, #3 27a2e702a2SDimitris Papastamos add x1, x1, x0 28a2e702a2SDimitris Papastamos br x1 29a2e702a2SDimitris Papastamos 30a2e702a2SDimitris Papastamos1: 31a2e702a2SDimitris Papastamos mrs x0, CPUAMEVCNTR0_EL0 32a2e702a2SDimitris Papastamos ret 33a2e702a2SDimitris Papastamos mrs x0, CPUAMEVCNTR1_EL0 34a2e702a2SDimitris Papastamos ret 35a2e702a2SDimitris Papastamos mrs x0, CPUAMEVCNTR2_EL0 36a2e702a2SDimitris Papastamos ret 37a2e702a2SDimitris Papastamos mrs x0, CPUAMEVCNTR3_EL0 38a2e702a2SDimitris Papastamos ret 39a2e702a2SDimitris Papastamos mrs x0, CPUAMEVCNTR4_EL0 40a2e702a2SDimitris Papastamos ret 41a2e702a2SDimitris Papastamosendfunc cpuamu_cnt_read 42a2e702a2SDimitris Papastamos 43a2e702a2SDimitris Papastamos/* 44*40daecc1SAntonio Nino Diaz * void cpuamu_cnt_write(unsigned int idx, uint64_t val); 45a2e702a2SDimitris Papastamos * 46a2e702a2SDimitris Papastamos * Given `idx`, write `val` to the corresponding AMU counter. 47a2e702a2SDimitris Papastamos */ 48a2e702a2SDimitris Papastamosfunc cpuamu_cnt_write 49a2e702a2SDimitris Papastamos adr x2, 1f 50a2e702a2SDimitris Papastamos lsl x0, x0, #3 51a2e702a2SDimitris Papastamos add x2, x2, x0 52a2e702a2SDimitris Papastamos br x2 53a2e702a2SDimitris Papastamos 54a2e702a2SDimitris Papastamos1: 55a2e702a2SDimitris Papastamos msr CPUAMEVCNTR0_EL0, x0 56a2e702a2SDimitris Papastamos ret 57a2e702a2SDimitris Papastamos msr CPUAMEVCNTR1_EL0, x0 58a2e702a2SDimitris Papastamos ret 59a2e702a2SDimitris Papastamos msr CPUAMEVCNTR2_EL0, x0 60a2e702a2SDimitris Papastamos ret 61a2e702a2SDimitris Papastamos msr CPUAMEVCNTR3_EL0, x0 62a2e702a2SDimitris Papastamos ret 63a2e702a2SDimitris Papastamos msr CPUAMEVCNTR4_EL0, x0 64a2e702a2SDimitris Papastamos ret 65a2e702a2SDimitris Papastamosendfunc cpuamu_cnt_write 66a2e702a2SDimitris Papastamos 67a2e702a2SDimitris Papastamos/* 68a2e702a2SDimitris Papastamos * unsigned int cpuamu_read_cpuamcntenset_el0(void); 69a2e702a2SDimitris Papastamos * 70a2e702a2SDimitris Papastamos * Read the `CPUAMCNTENSET_EL0` CPU register and return 71a2e702a2SDimitris Papastamos * it in `x0`. 72a2e702a2SDimitris Papastamos */ 73a2e702a2SDimitris Papastamosfunc cpuamu_read_cpuamcntenset_el0 74a2e702a2SDimitris Papastamos mrs x0, CPUAMCNTENSET_EL0 75a2e702a2SDimitris Papastamos ret 76a2e702a2SDimitris Papastamosendfunc cpuamu_read_cpuamcntenset_el0 77a2e702a2SDimitris Papastamos 78a2e702a2SDimitris Papastamos/* 79a2e702a2SDimitris Papastamos * unsigned int cpuamu_read_cpuamcntenclr_el0(void); 80a2e702a2SDimitris Papastamos * 81a2e702a2SDimitris Papastamos * Read the `CPUAMCNTENCLR_EL0` CPU register and return 82a2e702a2SDimitris Papastamos * it in `x0`. 83a2e702a2SDimitris Papastamos */ 84a2e702a2SDimitris Papastamosfunc cpuamu_read_cpuamcntenclr_el0 85a2e702a2SDimitris Papastamos mrs x0, CPUAMCNTENCLR_EL0 86a2e702a2SDimitris Papastamos ret 87a2e702a2SDimitris Papastamosendfunc cpuamu_read_cpuamcntenclr_el0 88a2e702a2SDimitris Papastamos 89a2e702a2SDimitris Papastamos/* 90a2e702a2SDimitris Papastamos * void cpuamu_write_cpuamcntenset_el0(unsigned int mask); 91a2e702a2SDimitris Papastamos * 92a2e702a2SDimitris Papastamos * Write `mask` to the `CPUAMCNTENSET_EL0` CPU register. 93a2e702a2SDimitris Papastamos */ 94a2e702a2SDimitris Papastamosfunc cpuamu_write_cpuamcntenset_el0 95a2e702a2SDimitris Papastamos msr CPUAMCNTENSET_EL0, x0 96a2e702a2SDimitris Papastamos ret 97a2e702a2SDimitris Papastamosendfunc cpuamu_write_cpuamcntenset_el0 98a2e702a2SDimitris Papastamos 99a2e702a2SDimitris Papastamos/* 100a2e702a2SDimitris Papastamos * void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); 101a2e702a2SDimitris Papastamos * 102a2e702a2SDimitris Papastamos * Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register. 103a2e702a2SDimitris Papastamos */ 104a2e702a2SDimitris Papastamosfunc cpuamu_write_cpuamcntenclr_el0 105a2e702a2SDimitris Papastamos msr CPUAMCNTENCLR_EL0, x0 106a2e702a2SDimitris Papastamos ret 107a2e702a2SDimitris Papastamosendfunc cpuamu_write_cpuamcntenclr_el0 108