1a2e702a2SDimitris Papastamos/* 2*4c700c15SGovindraj Raja * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. 3a2e702a2SDimitris Papastamos * 4a2e702a2SDimitris Papastamos * SPDX-License-Identifier: BSD-3-Clause 5a2e702a2SDimitris Papastamos */ 6a2e702a2SDimitris Papastamos 7a2e702a2SDimitris Papastamos#include <arch.h> 8a2e702a2SDimitris Papastamos#include <asm_macros.S> 9a2e702a2SDimitris Papastamos#include <cpuamu.h> 10a2e702a2SDimitris Papastamos 11a2e702a2SDimitris Papastamos .globl cpuamu_cnt_read 12a2e702a2SDimitris Papastamos .globl cpuamu_cnt_write 13a2e702a2SDimitris Papastamos .globl cpuamu_read_cpuamcntenset_el0 14a2e702a2SDimitris Papastamos .globl cpuamu_read_cpuamcntenclr_el0 15a2e702a2SDimitris Papastamos .globl cpuamu_write_cpuamcntenset_el0 16a2e702a2SDimitris Papastamos .globl cpuamu_write_cpuamcntenclr_el0 17a2e702a2SDimitris Papastamos 18a2e702a2SDimitris Papastamos/* 1940daecc1SAntonio Nino Diaz * uint64_t cpuamu_cnt_read(unsigned int idx); 20a2e702a2SDimitris Papastamos * 21a2e702a2SDimitris Papastamos * Given `idx`, read the corresponding AMU counter 22a2e702a2SDimitris Papastamos * and return it in `x0`. 23a2e702a2SDimitris Papastamos */ 24a2e702a2SDimitris Papastamosfunc cpuamu_cnt_read 25a2e702a2SDimitris Papastamos adr x1, 1f 269fc59639SAlexei Fedorov add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */ 279fc59639SAlexei Fedorov#if ENABLE_BTI 289fc59639SAlexei Fedorov add x1, x1, x0, lsl #2 /* + "bti j" instruction */ 299fc59639SAlexei Fedorov#endif 30a2e702a2SDimitris Papastamos br x1 31a2e702a2SDimitris Papastamos 329fc59639SAlexei Fedorov1: read CPUAMEVCNTR0_EL0 339fc59639SAlexei Fedorov read CPUAMEVCNTR1_EL0 349fc59639SAlexei Fedorov read CPUAMEVCNTR2_EL0 359fc59639SAlexei Fedorov read CPUAMEVCNTR3_EL0 369fc59639SAlexei Fedorov read CPUAMEVCNTR4_EL0 37a2e702a2SDimitris Papastamosendfunc cpuamu_cnt_read 38a2e702a2SDimitris Papastamos 39a2e702a2SDimitris Papastamos/* 4040daecc1SAntonio Nino Diaz * void cpuamu_cnt_write(unsigned int idx, uint64_t val); 41a2e702a2SDimitris Papastamos * 42a2e702a2SDimitris Papastamos * Given `idx`, write `val` to the corresponding AMU counter. 43a2e702a2SDimitris Papastamos */ 44a2e702a2SDimitris Papastamosfunc cpuamu_cnt_write 45a2e702a2SDimitris Papastamos adr x2, 1f 469fc59639SAlexei Fedorov add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */ 479fc59639SAlexei Fedorov#if ENABLE_BTI 489fc59639SAlexei Fedorov add x2, x2, x0, lsl #2 /* + "bti j" instruction */ 499fc59639SAlexei Fedorov#endif 50a2e702a2SDimitris Papastamos br x2 51a2e702a2SDimitris Papastamos 529fc59639SAlexei Fedorov1: write CPUAMEVCNTR0_EL0 539fc59639SAlexei Fedorov write CPUAMEVCNTR1_EL0 549fc59639SAlexei Fedorov write CPUAMEVCNTR2_EL0 559fc59639SAlexei Fedorov write CPUAMEVCNTR3_EL0 569fc59639SAlexei Fedorov write CPUAMEVCNTR4_EL0 57a2e702a2SDimitris Papastamosendfunc cpuamu_cnt_write 58a2e702a2SDimitris Papastamos 59a2e702a2SDimitris Papastamos/* 60a2e702a2SDimitris Papastamos * unsigned int cpuamu_read_cpuamcntenset_el0(void); 61a2e702a2SDimitris Papastamos * 62a2e702a2SDimitris Papastamos * Read the `CPUAMCNTENSET_EL0` CPU register and return 63a2e702a2SDimitris Papastamos * it in `x0`. 64a2e702a2SDimitris Papastamos */ 65a2e702a2SDimitris Papastamosfunc cpuamu_read_cpuamcntenset_el0 66a2e702a2SDimitris Papastamos mrs x0, CPUAMCNTENSET_EL0 67a2e702a2SDimitris Papastamos ret 68a2e702a2SDimitris Papastamosendfunc cpuamu_read_cpuamcntenset_el0 69a2e702a2SDimitris Papastamos 70a2e702a2SDimitris Papastamos/* 71a2e702a2SDimitris Papastamos * unsigned int cpuamu_read_cpuamcntenclr_el0(void); 72a2e702a2SDimitris Papastamos * 73a2e702a2SDimitris Papastamos * Read the `CPUAMCNTENCLR_EL0` CPU register and return 74a2e702a2SDimitris Papastamos * it in `x0`. 75a2e702a2SDimitris Papastamos */ 76a2e702a2SDimitris Papastamosfunc cpuamu_read_cpuamcntenclr_el0 77a2e702a2SDimitris Papastamos mrs x0, CPUAMCNTENCLR_EL0 78a2e702a2SDimitris Papastamos ret 79a2e702a2SDimitris Papastamosendfunc cpuamu_read_cpuamcntenclr_el0 80a2e702a2SDimitris Papastamos 81a2e702a2SDimitris Papastamos/* 82a2e702a2SDimitris Papastamos * void cpuamu_write_cpuamcntenset_el0(unsigned int mask); 83a2e702a2SDimitris Papastamos * 84a2e702a2SDimitris Papastamos * Write `mask` to the `CPUAMCNTENSET_EL0` CPU register. 85a2e702a2SDimitris Papastamos */ 86a2e702a2SDimitris Papastamosfunc cpuamu_write_cpuamcntenset_el0 87a2e702a2SDimitris Papastamos msr CPUAMCNTENSET_EL0, x0 88a2e702a2SDimitris Papastamos ret 89a2e702a2SDimitris Papastamosendfunc cpuamu_write_cpuamcntenset_el0 90a2e702a2SDimitris Papastamos 91a2e702a2SDimitris Papastamos/* 92a2e702a2SDimitris Papastamos * void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); 93a2e702a2SDimitris Papastamos * 94a2e702a2SDimitris Papastamos * Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register. 95a2e702a2SDimitris Papastamos */ 96a2e702a2SDimitris Papastamosfunc cpuamu_write_cpuamcntenclr_el0 97a2e702a2SDimitris Papastamos msr CPUAMCNTENCLR_EL0, x0 98a2e702a2SDimitris Papastamos ret 99a2e702a2SDimitris Papastamosendfunc cpuamu_write_cpuamcntenclr_el0 100