1 /* 2 * Copyright (c) 2018-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <cpuamu.h> 8 #include <lib/el3_runtime/pubsub_events.h> 9 #include <plat/common/platform.h> 10 11 #define CPUAMU_NR_COUNTERS 5U 12 13 struct cpuamu_ctx { 14 uint64_t cnts[CPUAMU_NR_COUNTERS]; 15 unsigned int mask; 16 }; 17 18 static struct cpuamu_ctx cpuamu_ctxs[PLATFORM_CORE_COUNT]; 19 20 void cpuamu_context_save(unsigned int nr_counters) 21 { 22 struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()]; 23 unsigned int i; 24 25 assert(nr_counters <= CPUAMU_NR_COUNTERS); 26 27 /* Save counter configuration */ 28 ctx->mask = cpuamu_read_cpuamcntenset_el0(); 29 30 /* Disable counters */ 31 cpuamu_write_cpuamcntenclr_el0(ctx->mask); 32 isb(); 33 34 /* Save counters */ 35 for (i = 0; i < nr_counters; i++) 36 ctx->cnts[i] = cpuamu_cnt_read(i); 37 } 38 39 void cpuamu_context_restore(unsigned int nr_counters) 40 { 41 struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()]; 42 unsigned int i; 43 44 assert(nr_counters <= CPUAMU_NR_COUNTERS); 45 46 /* 47 * Disable counters. They were enabled early in the 48 * CPU reset function. 49 */ 50 cpuamu_write_cpuamcntenclr_el0(ctx->mask); 51 isb(); 52 53 /* Restore counters */ 54 for (i = 0; i < nr_counters; i++) 55 cpuamu_cnt_write(i, ctx->cnts[i]); 56 isb(); 57 58 /* Restore counter configuration */ 59 cpuamu_write_cpuamcntenset_el0(ctx->mask); 60 } 61