1/* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <assert_macros.S> 34#include <cpu_macros.S> 35#if IMAGE_BL31 36#include <cpu_data.h> 37#endif 38 39 /* Reset fn is needed in BL at reset vector */ 40#if IMAGE_BL1 || IMAGE_BL31 41 /* 42 * The reset handler common to all platforms. After a matching 43 * cpu_ops structure entry is found, the correponding reset_handler 44 * in the cpu_ops is invoked. 45 */ 46 .globl reset_handler 47func reset_handler 48 mov x19, x30 49 50 bl plat_reset_handler 51 52 /* Get the matching cpu_ops pointer */ 53 bl get_cpu_ops_ptr 54#if ASM_ASSERTION 55 cmp x0, #0 56 ASM_ASSERT(ne) 57#endif 58 59 /* Get the cpu_ops reset handler */ 60 ldr x2, [x0, #CPU_RESET_FUNC] 61 mov x30, x19 62 cbz x2, 1f 63 br x2 641: 65 ret 66 67#endif /* IMAGE_BL1 || IMAGE_BL31 */ 68 69#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ 70 /* 71 * The prepare core power down function for all platforms. After 72 * the cpu_ops pointer is retrieved from cpu_data, the corresponding 73 * pwr_dwn_core in the cpu_ops is invoked. 74 */ 75 .globl prepare_core_pwr_dwn 76func prepare_core_pwr_dwn 77 mrs x1, tpidr_el3 78 ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] 79#if ASM_ASSERTION 80 cmp x0, #0 81 ASM_ASSERT(ne) 82#endif 83 84 /* Get the cpu_ops core_pwr_dwn handler */ 85 ldr x1, [x0, #CPU_PWR_DWN_CORE] 86 br x1 87 88 /* 89 * The prepare cluster power down function for all platforms. After 90 * the cpu_ops pointer is retrieved from cpu_data, the corresponding 91 * pwr_dwn_cluster in the cpu_ops is invoked. 92 */ 93 .globl prepare_cluster_pwr_dwn 94func prepare_cluster_pwr_dwn 95 mrs x1, tpidr_el3 96 ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] 97#if ASM_ASSERTION 98 cmp x0, #0 99 ASM_ASSERT(ne) 100#endif 101 102 /* Get the cpu_ops cluster_pwr_dwn handler */ 103 ldr x1, [x0, #CPU_PWR_DWN_CLUSTER] 104 br x1 105 106 107 /* 108 * Initializes the cpu_ops_ptr if not already initialized 109 * in cpu_data. This can be called without a runtime stack. 110 * clobbers: x0 - x6, x10 111 */ 112 .globl init_cpu_ops 113func init_cpu_ops 114 mrs x6, tpidr_el3 115 ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR] 116 cbnz x0, 1f 117 mov x10, x30 118 bl get_cpu_ops_ptr 119#if ASM_ASSERTION 120 cmp x0, #0 121 ASM_ASSERT(ne) 122#endif 123 str x0, [x6, #CPU_DATA_CPU_OPS_PTR]! 124 125 /* 126 * Make sure that any pre-fetched cache copies are invalidated. 127 * Ensure that we are running with cache disable else we 128 * invalidate our own update. 129 */ 130#if ASM_ASSERTION 131 mrs x1, sctlr_el3 132 tst x1, #SCTLR_C_BIT 133 ASM_ASSERT(eq) 134#endif 135 dc ivac, x6 136 mov x30, x10 1371: 138 ret 139#endif /* IMAGE_BL31 */ 140 141#if IMAGE_BL31 && CRASH_REPORTING 142 /* 143 * The cpu specific registers which need to be reported in a crash 144 * are reported via cpu_ops cpu_reg_dump function. After a matching 145 * cpu_ops structure entry is found, the correponding cpu_reg_dump 146 * in the cpu_ops is invoked. 147 */ 148 .globl do_cpu_reg_dump 149func do_cpu_reg_dump 150 mov x16, x30 151 152 /* Get the matching cpu_ops pointer */ 153 bl get_cpu_ops_ptr 154 cbz x0, 1f 155 156 /* Get the cpu_ops cpu_reg_dump */ 157 ldr x2, [x0, #CPU_REG_DUMP] 158 cbz x2, 1f 159 blr x2 1601: 161 mov x30, x16 162 ret 163#endif 164 165 /* 166 * The below function returns the cpu_ops structure matching the 167 * midr of the core. It reads the MIDR_EL1 and finds the matching 168 * entry in cpu_ops entries. Only the implementation and part number 169 * are used to match the entries. 170 * Return : 171 * x0 - The matching cpu_ops pointer on Success 172 * x0 - 0 on failure. 173 * Clobbers : x0 - x5 174 */ 175 .globl get_cpu_ops_ptr 176func get_cpu_ops_ptr 177 /* Get the cpu_ops start and end locations */ 178 adr x4, (__CPU_OPS_START__ + CPU_MIDR) 179 adr x5, (__CPU_OPS_END__ + CPU_MIDR) 180 181 /* Initialize the return parameter */ 182 mov x0, #0 183 184 /* Read the MIDR_EL1 */ 185 mrs x2, midr_el1 186 mov_imm x3, CPU_IMPL_PN_MASK 187 188 /* Retain only the implementation and part number using mask */ 189 and w2, w2, w3 1901: 191 /* Check if we have reached end of list */ 192 cmp x4, x5 193 b.eq error_exit 194 195 /* load the midr from the cpu_ops */ 196 ldr x1, [x4], #CPU_OPS_SIZE 197 and w1, w1, w3 198 199 /* Check if midr matches to midr of this core */ 200 cmp w1, w2 201 b.ne 1b 202 203 /* Subtract the increment and offset to get the cpu-ops pointer */ 204 sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR) 205error_exit: 206 ret 207 208#if DEBUG 209 /* 210 * This function prints a warning message to the crash console 211 * if the CPU revision/part number does not match the errata 212 * workaround enabled in the build. 213 * Clobber: x30, x0 - x5 214 */ 215.section .rodata.rev_warn_str, "aS" 216rev_warn_str: 217 .asciz "Warning: Skipping Errata workaround for non matching CPU revision number.\n" 218 219 .globl print_revision_warning 220func print_revision_warning 221 mov x5, x30 222 /* Ensure the console is initialized */ 223 bl plat_crash_console_init 224 /* Check if the console is initialized */ 225 cbz x0, 1f 226 /* The console is initialized */ 227 adr x4, rev_warn_str 228 bl asm_print_str 2291: 230 ret x5 231#endif 232 233