1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x925.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 25workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 26 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) 27workaround_reset_end cortex_x925, CVE(2024, 5660) 28 29check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) 30 31workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 32 /* --------------------------------- 33 * Sets BIT41 of CPUACTLR6_EL1 which 34 * disables L1 Data cache prefetcher 35 * --------------------------------- 36 */ 37 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 38workaround_reset_end cortex_x925, CVE(2024, 7881) 39 40check_erratum_chosen cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 41 42cpu_reset_func_start cortex_x925 43 /* Disable speculative loads */ 44 msr SSBS, xzr 45cpu_reset_func_end cortex_x925 46 47 /* ---------------------------------------------------- 48 * HW will do the cache maintenance while powering down 49 * ---------------------------------------------------- 50 */ 51func cortex_x925_core_pwr_dwn 52 /* --------------------------------------------------- 53 * Enable CPU power down bit in power control register 54 * --------------------------------------------------- 55 */ 56 sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 57 isb 58 ret 59endfunc cortex_x925_core_pwr_dwn 60 61 /* --------------------------------------------- 62 * This function provides Cortex-X925 specific 63 * register information for crash reporting. 64 * It needs to return with x6 pointing to 65 * a list of register names in ascii and 66 * x8 - x15 having values of registers to be 67 * reported. 68 * --------------------------------------------- 69 */ 70.section .rodata.cortex_x925_regs, "aS" 71cortex_x925_regs: /* The ascii list of register names to be reported */ 72 .asciz "cpuectlr_el1", "" 73 74func cortex_x925_cpu_reg_dump 75 adr x6, cortex_x925_regs 76 mrs x8, CORTEX_X925_CPUECTLR_EL1 77 ret 78endfunc cortex_x925_cpu_reg_dump 79 80declare_cpu_ops_wa_4 cortex_x925, CORTEX_X925_MIDR, \ 81 cortex_x925_reset_func, \ 82 CPU_NO_EXTRA1_FUNC, \ 83 CPU_NO_EXTRA2_FUNC, \ 84 CPU_NO_EXTRA3_FUNC, \ 85 check_erratum_cortex_x925_7881, \ 86 cortex_x925_core_pwr_dwn 87