1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x925.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_x925 26 27workaround_reset_start cortex_x925, ERRATUM(2900952), ERRATA_DSU_2900952 28 errata_dsu_2900952_wa_apply 29workaround_reset_end cortex_x925, ERRATUM(2900952) 30 31check_erratum_custom_start cortex_x925, ERRATUM(2900952) 32 check_errata_dsu_2900952_applies 33 ret 34check_erratum_custom_end cortex_x925, ERRATUM(2900952) 35 36add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747 37 38check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1) 39 40workaround_reset_start cortex_x925, ERRATUM(2963999), ERRATA_X925_2963999 41 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 42 ldr x0, =0x0 43 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 44 ldr x0, =0xd5380000 45 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 46 ldr x0, =0xFFFFFF40 47 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 48 ldr x0, =0x000080010033f 49 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 50 isb 51workaround_reset_end cortex_x925, ERRATUM(2963999) 52 53check_erratum_ls cortex_x925, ERRATUM(2963999), CPU_REV(0, 0) 54 55/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 56workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 57 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) 58workaround_reset_end cortex_x925, CVE(2024, 5660) 59 60check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) 61 62workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 63 /* --------------------------------- 64 * Sets BIT41 of CPUACTLR6_EL1 which 65 * disables L1 Data cache prefetcher 66 * --------------------------------- 67 */ 68 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 69workaround_reset_end cortex_x925, CVE(2024, 7881) 70 71check_erratum_chosen cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 72 73cpu_reset_func_start cortex_x925 74 /* Disable speculative loads */ 75 msr SSBS, xzr 76 enable_mpmm 77cpu_reset_func_end cortex_x925 78 79 /* ---------------------------------------------------- 80 * HW will do the cache maintenance while powering down 81 * ---------------------------------------------------- 82 */ 83func cortex_x925_core_pwr_dwn 84 /* --------------------------------------------------- 85 * Enable CPU power down bit in power control register 86 * --------------------------------------------------- 87 */ 88 sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 89 isb 90 ret 91endfunc cortex_x925_core_pwr_dwn 92 93 /* --------------------------------------------- 94 * This function provides Cortex-X925 specific 95 * register information for crash reporting. 96 * It needs to return with x6 pointing to 97 * a list of register names in ascii and 98 * x8 - x15 having values of registers to be 99 * reported. 100 * --------------------------------------------- 101 */ 102.section .rodata.cortex_x925_regs, "aS" 103cortex_x925_regs: /* The ascii list of register names to be reported */ 104 .asciz "cpuectlr_el1", "" 105 106func cortex_x925_cpu_reg_dump 107 adr x6, cortex_x925_regs 108 mrs x8, CORTEX_X925_CPUECTLR_EL1 109 ret 110endfunc cortex_x925_cpu_reg_dump 111 112declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \ 113 cortex_x925_reset_func, \ 114 cortex_x925_core_pwr_dwn 115