1/* 2 * Copyright (c) 2023-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x925.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <wa_cve_2025_0647_cpprctx.h> 14 15#include <plat_macros.S> 16 17/* Hardware handled coherency */ 18#if HW_ASSISTED_COHERENCY == 0 19#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled" 20#endif 21 22/* 64-bit only core */ 23#if CTX_INCLUDE_AARCH32_REGS == 1 24#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 25#endif 26 27cpu_reset_prologue cortex_x925 28 29workaround_reset_start cortex_x925, ERRATUM(2900952), ERRATA_DSU_2900952 30 errata_dsu_2900952_wa_apply 31workaround_reset_end cortex_x925, ERRATUM(2900952) 32 33check_erratum_custom_start cortex_x925, ERRATUM(2900952) 34 check_errata_dsu_2900952_applies 35 ret 36check_erratum_custom_end cortex_x925, ERRATUM(2900952) 37 38add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747 39 40.global check_erratum_cortex_x925_3701747 41check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1) 42 43workaround_reset_start cortex_x925, ERRATUM(2921199), ERRATA_X925_2921199 44 sysreg_bit_set CORTEX_X925_CPUACTLR5_EL1, BIT(14) 45workaround_reset_end cortex_x925, ERRATUM(2921199) 46 47check_erratum_ls cortex_x925, ERRATUM(2921199), CPU_REV(0, 0) 48 49workaround_reset_start cortex_x925, ERRATUM(2922378), ERRATA_X925_2922378 50 sysreg_bitfield_insert CORTEX_X925_CPUACTLR4_EL1, CORTEX_X925_CPUACTLR4_EL1_BHB_BIT, \ 51 CORTEX_X925_CPUACTLR4_EL1_BHB_SHIFT, CORTEX_X925_CPUACTLR4_EL1_BHB_WIDTH 52workaround_reset_end cortex_x925, ERRATUM(2922378) 53 54check_erratum_ls cortex_x925, ERRATUM(2922378), CPU_REV(0, 0) 55 56workaround_reset_start cortex_x925, ERRATUM(2933290), ERRATA_X925_2933290 57 sysreg_bit_set CORTEX_X925_CPUACTLR5_EL1, BIT(42) 58workaround_reset_end cortex_x925, ERRATUM(2933290) 59 60check_erratum_ls cortex_x925, ERRATUM(2933290), CPU_REV(0, 0) 61 62workaround_reset_start cortex_x925, ERRATUM(2963999), ERRATA_X925_2963999 63 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 64 ldr x0, =0x0 65 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 66 ldr x0, =0xd5380000 67 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 68 ldr x0, =0xFFFFFF40 69 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 70 ldr x0, =0x000080010033f 71 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 72 isb 73workaround_reset_end cortex_x925, ERRATUM(2963999) 74 75check_erratum_ls cortex_x925, ERRATUM(2963999), CPU_REV(0, 0) 76 77workaround_runtime_start cortex_x925, ERRATUM(3324334), ERRATA_X925_3324334 78 speculation_barrier 79workaround_runtime_end cortex_x925, ERRATUM(3324334) 80 81check_erratum_ls cortex_x925, ERRATUM(3324334), CPU_REV(0, 1) 82 83workaround_reset_start cortex_x925, ERRATUM(3692980), ERRATA_X925_3692980 84 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 85workaround_reset_end cortex_x925, ERRATUM(3692980) 86 87check_erratum_ls cortex_x925, ERRATUM(3692980), CPU_REV(0, 1) 88 89workaround_reset_start cortex_x925, ERRATUM(3730893), ERRATA_X925_3730893 90 sysreg_bitfield_insert CORTEX_X925_CPUACTLR_EL1, CORTEX_X925_CPUACTLR_EL1_LOAD_BIT, \ 91 CORTEX_X925_CPUACTLR_EL1_LOAD_SHIFT, CORTEX_X925_CPUACTLR_EL1_LOAD_WIDTH 92workaround_reset_end cortex_x925, ERRATUM(3730893) 93 94check_erratum_ls cortex_x925, ERRATUM(3730893), CPU_REV(0, 1) 95 96workaround_reset_start cortex_x925, ERRATUM(3865185), ERRATA_X925_3865185 97 sysreg_bit_set CORTEX_X925_CPUACTLR2_EL1, BIT(22) 98workaround_reset_end cortex_x925, ERRATUM(3865185) 99 100check_erratum_ls cortex_x925, ERRATUM(3865185), CPU_REV(0, 1) 101 102/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 103workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 104 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) 105workaround_reset_end cortex_x925, CVE(2024, 5660) 106 107check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) 108 109 /* ---------------------------------------------------------------- 110 * CVE-2024-7881 is mitigated for Cortex-X925 using erratum 3692980 111 * workaround by disabling the affected prefetcher setting 112 * CPUACTLR6_EL1[41]. 113 * ---------------------------------------------------------------- 114 */ 115workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 116 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 117workaround_reset_end cortex_x925, CVE(2024, 7881) 118 119check_erratum_ls cortex_x925, CVE(2024, 7881), CPU_REV(0, 1) 120 121 /* 122 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 123 * Enables mitigation for CVE-2025-0647. 124 */ 125workaround_reset_start cortex_x925, CVE(2025, 647), WORKAROUND_CVE_2025_0647 126 mov x0, #WA_PATCH_SLOT(3) 127 bl wa_cve_2025_0647_instruction_patch 128workaround_reset_end cortex_x925, CVE(2025, 647) 129 130check_erratum_chosen cortex_x925, CVE(2025, 647), WORKAROUND_CVE_2025_0647 131 132#if WORKAROUND_CVE_2025_0647 133func cortex_x925_impl_defined_el3_handler 134 mov x0, #0 135 136 /* See if this call came from trap handler. */ 137 cmp x1, #EC_IMP_DEF_EL3 138 bne wa_cve_2025_0647_do_cpp_wa 139 orr x0, x0, #WA_IS_TRAP_HANDLER 140 b wa_cve_2025_0647_do_cpp_wa 141endfunc cortex_x925_impl_defined_el3_handler 142#endif 143 144cpu_reset_func_start cortex_x925 145 /* Disable speculative loads */ 146 msr SSBS, xzr 147 apply_erratum cortex_x925, ERRATUM(3324334), ERRATA_X925_3324334 148 enable_mpmm 149cpu_reset_func_end cortex_x925 150 151 /* ---------------------------------------------------- 152 * HW will do the cache maintenance while powering down 153 * ---------------------------------------------------- 154 */ 155func cortex_x925_core_pwr_dwn 156 /* --------------------------------------------------- 157 * Enable CPU power down bit in power control register 158 * --------------------------------------------------- 159 */ 160 sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 161 isb 162 ret 163endfunc cortex_x925_core_pwr_dwn 164 165 /* --------------------------------------------- 166 * This function provides Cortex-X925 specific 167 * register information for crash reporting. 168 * It needs to return with x6 pointing to 169 * a list of register names in ascii and 170 * x8 - x15 having values of registers to be 171 * reported. 172 * --------------------------------------------- 173 */ 174.section .rodata.cortex_x925_regs, "aS" 175cortex_x925_regs: /* The ascii list of register names to be reported */ 176 .asciz "cpuectlr_el1", "" 177 178func cortex_x925_cpu_reg_dump 179 adr x6, cortex_x925_regs 180 mrs x8, CORTEX_X925_CPUECTLR_EL1 181 ret 182endfunc cortex_x925_cpu_reg_dump 183 184#if WORKAROUND_CVE_2025_0647 185declare_cpu_ops_eh cortex_x925, CORTEX_X925_MIDR, \ 186 cortex_x925_reset_func, \ 187 cortex_x925_impl_defined_el3_handler, \ 188 cortex_x925_core_pwr_dwn 189#else 190declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \ 191 cortex_x925_reset_func, \ 192 cortex_x925_core_pwr_dwn 193#endif 194 195