1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x925.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_x925 26 27workaround_reset_start cortex_x925, ERRATUM(2900952), ERRATA_DSU_2900952 28 errata_dsu_2900952_wa_apply 29workaround_reset_end cortex_x925, ERRATUM(2900952) 30 31check_erratum_custom_start cortex_x925, ERRATUM(2900952) 32 check_errata_dsu_2900952_applies 33 ret 34check_erratum_custom_end cortex_x925, ERRATUM(2900952) 35 36add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747 37 38.global check_erratum_cortex_x925_3701747 39check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1) 40 41workaround_reset_start cortex_x925, ERRATUM(2963999), ERRATA_X925_2963999 42 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 43 ldr x0, =0x0 44 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 45 ldr x0, =0xd5380000 46 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 47 ldr x0, =0xFFFFFF40 48 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 49 ldr x0, =0x000080010033f 50 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 51 isb 52workaround_reset_end cortex_x925, ERRATUM(2963999) 53 54check_erratum_ls cortex_x925, ERRATUM(2963999), CPU_REV(0, 0) 55 56/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 57workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 58 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) 59workaround_reset_end cortex_x925, CVE(2024, 5660) 60 61check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) 62 63workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 64 /* --------------------------------- 65 * Sets BIT41 of CPUACTLR6_EL1 which 66 * disables L1 Data cache prefetcher 67 * --------------------------------- 68 */ 69 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 70workaround_reset_end cortex_x925, CVE(2024, 7881) 71 72check_erratum_chosen cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 73 74cpu_reset_func_start cortex_x925 75 /* Disable speculative loads */ 76 msr SSBS, xzr 77 enable_mpmm 78cpu_reset_func_end cortex_x925 79 80 /* ---------------------------------------------------- 81 * HW will do the cache maintenance while powering down 82 * ---------------------------------------------------- 83 */ 84func cortex_x925_core_pwr_dwn 85 /* --------------------------------------------------- 86 * Enable CPU power down bit in power control register 87 * --------------------------------------------------- 88 */ 89 sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 90 isb 91 ret 92endfunc cortex_x925_core_pwr_dwn 93 94 /* --------------------------------------------- 95 * This function provides Cortex-X925 specific 96 * register information for crash reporting. 97 * It needs to return with x6 pointing to 98 * a list of register names in ascii and 99 * x8 - x15 having values of registers to be 100 * reported. 101 * --------------------------------------------- 102 */ 103.section .rodata.cortex_x925_regs, "aS" 104cortex_x925_regs: /* The ascii list of register names to be reported */ 105 .asciz "cpuectlr_el1", "" 106 107func cortex_x925_cpu_reg_dump 108 adr x6, cortex_x925_regs 109 mrs x8, CORTEX_X925_CPUECTLR_EL1 110 ret 111endfunc cortex_x925_cpu_reg_dump 112 113declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \ 114 cortex_x925_reset_func, \ 115 cortex_x925_core_pwr_dwn 116