1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x925.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24.global check_erratum_cortex_x925_3701747 25 26add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747, NO_APPLY_AT_RESET 27 28check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1) 29 30/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 31workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 32 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) 33workaround_reset_end cortex_x925, CVE(2024, 5660) 34 35check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) 36 37workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 38 /* --------------------------------- 39 * Sets BIT41 of CPUACTLR6_EL1 which 40 * disables L1 Data cache prefetcher 41 * --------------------------------- 42 */ 43 sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41) 44workaround_reset_end cortex_x925, CVE(2024, 7881) 45 46check_erratum_chosen cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 47 48cpu_reset_func_start cortex_x925 49 /* Disable speculative loads */ 50 msr SSBS, xzr 51cpu_reset_func_end cortex_x925 52 53 /* ---------------------------------------------------- 54 * HW will do the cache maintenance while powering down 55 * ---------------------------------------------------- 56 */ 57func cortex_x925_core_pwr_dwn 58 /* --------------------------------------------------- 59 * Enable CPU power down bit in power control register 60 * --------------------------------------------------- 61 */ 62 sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 63 isb 64 ret 65endfunc cortex_x925_core_pwr_dwn 66 67 /* --------------------------------------------- 68 * This function provides Cortex-X925 specific 69 * register information for crash reporting. 70 * It needs to return with x6 pointing to 71 * a list of register names in ascii and 72 * x8 - x15 having values of registers to be 73 * reported. 74 * --------------------------------------------- 75 */ 76.section .rodata.cortex_x925_regs, "aS" 77cortex_x925_regs: /* The ascii list of register names to be reported */ 78 .asciz "cpuectlr_el1", "" 79 80func cortex_x925_cpu_reg_dump 81 adr x6, cortex_x925_regs 82 mrs x8, CORTEX_X925_CPUECTLR_EL1 83 ret 84endfunc cortex_x925_cpu_reg_dump 85 86declare_cpu_ops_wa_4 cortex_x925, CORTEX_X925_MIDR, \ 87 cortex_x925_reset_func, \ 88 CPU_NO_EXTRA1_FUNC, \ 89 CPU_NO_EXTRA2_FUNC, \ 90 CPU_NO_EXTRA3_FUNC, \ 91 check_erratum_cortex_x925_7881, \ 92 cortex_x925_core_pwr_dwn 93