1/* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x925.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 25workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 26 sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46) 27workaround_reset_end cortex_x925, CVE(2024, 5660) 28 29check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) 30 31cpu_reset_func_start cortex_x925 32 /* Disable speculative loads */ 33 msr SSBS, xzr 34cpu_reset_func_end cortex_x925 35 36 /* ---------------------------------------------------- 37 * HW will do the cache maintenance while powering down 38 * ---------------------------------------------------- 39 */ 40func cortex_x925_core_pwr_dwn 41 /* --------------------------------------------------- 42 * Enable CPU power down bit in power control register 43 * --------------------------------------------------- 44 */ 45 sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 46 isb 47 ret 48endfunc cortex_x925_core_pwr_dwn 49 50 /* --------------------------------------------- 51 * This function provides Cortex-X925 specific 52 * register information for crash reporting. 53 * It needs to return with x6 pointing to 54 * a list of register names in ascii and 55 * x8 - x15 having values of registers to be 56 * reported. 57 * --------------------------------------------- 58 */ 59.section .rodata.cortex_x925_regs, "aS" 60cortex_x925_regs: /* The ascii list of register names to be reported */ 61 .asciz "cpuectlr_el1", "" 62 63func cortex_x925_cpu_reg_dump 64 adr x6, cortex_x925_regs 65 mrs x8, CORTEX_X925_CPUECTLR_EL1 66 ret 67endfunc cortex_x925_cpu_reg_dump 68 69declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \ 70 cortex_x925_reset_func, \ 71 cortex_x925_core_pwr_dwn 72