1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue cortex_x4 26 27.global check_erratum_cortex_x4_2726228 28.global check_erratum_cortex_x4_3701758 29 30#if WORKAROUND_CVE_2022_23960 31 wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 32#endif /* WORKAROUND_CVE_2022_23960 */ 33 34add_erratum_entry cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228 35 36check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1) 37 38/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 39workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 40 sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46) 41workaround_reset_end cortex_x4, CVE(2024, 5660) 42 43check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2) 44 45workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 46 /* dsb before isb of power down sequence */ 47 dsb sy 48workaround_runtime_end cortex_x4, ERRATUM(2740089) 49 50check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 51 52workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018 53 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 54workaround_reset_end cortex_x4, ERRATUM(2763018) 55 56check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1) 57 58workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013 59 mrs x1, id_aa64pfr1_el1 60 ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 61 cbz x2, #1f 62 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 631: 64workaround_reset_end cortex_x4, ERRATUM(2816013) 65 66check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1) 67 68workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503 69 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8) 70workaround_reset_end cortex_x4, ERRATUM(2897503) 71 72check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1) 73 74workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985 75 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10)) 76workaround_reset_end cortex_x4, ERRATUM(2923985) 77 78check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1) 79 80workaround_reset_start cortex_x4, ERRATUM(2957258), ERRATA_X4_2957258 81 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 82 ldr x0, =0x1 83 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 84 ldr x0, =0xd5380000 85 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 86 ldr x0, =0xFFFFFF40 87 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 88 ldr x0, =0x000080010033f 89 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 90 isb 91workaround_reset_end cortex_x4, ERRATUM(2957258) 92 93check_erratum_ls cortex_x4, ERRATUM(2957258), CPU_REV(0, 1) 94 95workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789 96 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14) 97 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13) 98 sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52) 99workaround_reset_end cortex_x4, ERRATUM(3076789) 100 101check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1) 102 103workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 104#if IMAGE_BL31 105 /* 106 * The Cortex X4 generic vectors are overridden to apply errata 107 * mitigation on exception entry from lower ELs. 108 */ 109 override_vector_table wa_cve_vbar_cortex_x4 110#endif /* IMAGE_BL31 */ 111workaround_reset_end cortex_x4, CVE(2022, 23960) 112 113check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 114 115workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 116 /* --------------------------------- 117 * Sets BIT41 of CPUACTLR6_EL1 which 118 * disables L1 Data cache prefetcher 119 * --------------------------------- 120 */ 121 sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41) 122workaround_reset_end cortex_x4, CVE(2024, 7881) 123 124check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 125 126add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758 127 128check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3) 129 130cpu_reset_func_start cortex_x4 131 /* Disable speculative loads */ 132 msr SSBS, xzr 133 enable_mpmm 134cpu_reset_func_end cortex_x4 135 136 /* ---------------------------------------------------- 137 * HW will do the cache maintenance while powering down 138 * ---------------------------------------------------- 139 */ 140func cortex_x4_core_pwr_dwn 141 /* --------------------------------------------------- 142 * Enable CPU power down bit in power control register 143 * --------------------------------------------------- 144 */ 145 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 146 147 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV 148 149 isb 150 ret 151endfunc cortex_x4_core_pwr_dwn 152 153 /* --------------------------------------------- 154 * This function provides Cortex X4-specific 155 * register information for crash reporting. 156 * It needs to return with x6 pointing to 157 * a list of register names in ascii and 158 * x8 - x15 having values of registers to be 159 * reported. 160 * --------------------------------------------- 161 */ 162.section .rodata.cortex_x4_regs, "aS" 163cortex_x4_regs: /* The ascii list of register names to be reported */ 164 .asciz "cpuectlr_el1", "" 165 166func cortex_x4_cpu_reg_dump 167 adr x6, cortex_x4_regs 168 mrs x8, CORTEX_X4_CPUECTLR_EL1 169 ret 170endfunc cortex_x4_cpu_reg_dump 171 172declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \ 173 cortex_x4_reset_func, \ 174 CPU_NO_EXTRA1_FUNC, \ 175 CPU_NO_EXTRA2_FUNC, \ 176 CPU_NO_EXTRA3_FUNC, \ 177 check_erratum_cortex_x4_7881, \ 178 cortex_x4_core_pwr_dwn 179