1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26cpu_reset_prologue cortex_x4 27 28.global check_erratum_cortex_x4_2726228 29.global check_erratum_cortex_x4_3701758 30 31add_erratum_entry cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228 32 33check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1) 34 35workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 36 /* dsb before isb of power down sequence */ 37 dsb sy 38workaround_runtime_end cortex_x4, ERRATUM(2740089) 39 40check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 41 42workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018 43 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 44workaround_reset_end cortex_x4, ERRATUM(2763018) 45 46check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1) 47 48workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013 49 mrs x1, id_aa64pfr1_el1 50 ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 51 cbz x2, #1f 52 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 531: 54workaround_reset_end cortex_x4, ERRATUM(2816013) 55 56check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1) 57 58workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503 59 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8) 60workaround_reset_end cortex_x4, ERRATUM(2897503) 61 62check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1) 63 64workaround_reset_start cortex_x4, ERRATUM(2900952), ERRATA_DSU_2900952 65 errata_dsu_2900952_wa_apply 66workaround_reset_end cortex_x4, ERRATUM(2900952) 67 68check_erratum_custom_start cortex_x4, ERRATUM(2900952) 69 check_errata_dsu_2900952_applies 70 ret 71check_erratum_custom_end cortex_x4, ERRATUM(2900952) 72 73workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985 74 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10)) 75workaround_reset_end cortex_x4, ERRATUM(2923985) 76 77check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1) 78 79workaround_reset_start cortex_x4, ERRATUM(2957258), ERRATA_X4_2957258 80 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 81 ldr x0, =0x1 82 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 83 ldr x0, =0xd5380000 84 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 85 ldr x0, =0xFFFFFF40 86 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 87 ldr x0, =0x000080010033f 88 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 89 isb 90workaround_reset_end cortex_x4, ERRATUM(2957258) 91 92check_erratum_ls cortex_x4, ERRATUM(2957258), CPU_REV(0, 1) 93 94workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789 95 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14) 96 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13) 97 sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52) 98workaround_reset_end cortex_x4, ERRATUM(3076789) 99 100check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1) 101 102workaround_reset_start cortex_x4, ERRATUM(3133195), ERRATA_X4_3133195 103 ldr x0,=0x2 104 msr s3_6_c15_c8_0,x0 /* msr cpupselr_el3, x0 */ 105 ldr x0,=0xd503225f 106 msr s3_6_c15_c8_2,x0 /* msr cpupor_el3, x0 */ 107 ldr x0,=0xffffffff 108 msr s3_6_c15_c8_3,x0 /* msr cpupmr_el3, x0 */ 109 ldr x0,=0x00000000404003fd 110 msr s3_6_c15_c8_1,x0 /* msr cpupcr_el3, x0 */ 111workaround_reset_end cortex_x4, ERRATUM(3133195) 112 113check_erratum_range cortex_x4, ERRATUM(3133195), CPU_REV(0, 2), CPU_REV(0, 2) 114 115add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758 116 117check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3) 118 119workaround_reset_start cortex_x4, ERRATUM(3887999), ERRATA_X4_3887999 120 sysreg_bit_set CORTEX_X4_CPUACTLR2_EL1, BIT(22) 121workaround_reset_end cortex_x4, ERRATUM(3887999) 122 123check_erratum_ls cortex_x4, ERRATUM(3887999), CPU_REV(0, 3) 124 125/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 126workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 127 sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46) 128workaround_reset_end cortex_x4, CVE(2024, 5660) 129 130check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2) 131 132workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 133 /* --------------------------------- 134 * Sets BIT41 of CPUACTLR6_EL1 which 135 * disables L1 Data cache prefetcher 136 * --------------------------------- 137 */ 138 sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41) 139workaround_reset_end cortex_x4, CVE(2024, 7881) 140 141check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 142 143cpu_reset_func_start cortex_x4 144 /* Disable speculative loads */ 145 msr SSBS, xzr 146 enable_mpmm 147cpu_reset_func_end cortex_x4 148 149 /* ---------------------------------------------------- 150 * HW will do the cache maintenance while powering down 151 * ---------------------------------------------------- 152 */ 153func cortex_x4_core_pwr_dwn 154 /* --------------------------------------------------- 155 * Enable CPU power down bit in power control register 156 * --------------------------------------------------- 157 */ 158 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 159 160 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 161 162 isb 163 ret 164endfunc cortex_x4_core_pwr_dwn 165 166 /* --------------------------------------------- 167 * This function provides Cortex X4-specific 168 * register information for crash reporting. 169 * It needs to return with x6 pointing to 170 * a list of register names in ascii and 171 * x8 - x15 having values of registers to be 172 * reported. 173 * --------------------------------------------- 174 */ 175.section .rodata.cortex_x4_regs, "aS" 176cortex_x4_regs: /* The ascii list of register names to be reported */ 177 .asciz "cpuectlr_el1", "" 178 179func cortex_x4_cpu_reg_dump 180 adr x6, cortex_x4_regs 181 mrs x8, CORTEX_X4_CPUECTLR_EL1 182 ret 183endfunc cortex_x4_cpu_reg_dump 184 185declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \ 186 cortex_x4_reset_func, \ 187 cortex_x4_core_pwr_dwn 188