1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x4.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_x4_2726228 26.global check_erratum_cortex_x4_3701758 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32workaround_runtime_start cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228, CORTEX_X4_MIDR 33workaround_runtime_end cortex_x4, ERRATUM(2726228) 34 35check_erratum_custom_start cortex_x4, ERRATUM(2726228) 36 37 /* This erratum needs to be enabled for r0p0 and r0p1. 38 * Check if revision is less than or equal to r0p1. 39 */ 40 41#if ERRATA_X4_2726228 42 mov x1, #1 43 b cpu_rev_var_ls 44#else 45 mov x0, #ERRATA_MISSING 46#endif 47 ret 48check_erratum_custom_end cortex_x4, ERRATUM(2726228) 49 50/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 51workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 52 sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46) 53workaround_reset_end cortex_x4, CVE(2024, 5660) 54 55check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2) 56 57workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089 58 /* dsb before isb of power down sequence */ 59 dsb sy 60workaround_runtime_end cortex_x4, ERRATUM(2740089) 61 62check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1) 63 64workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018 65 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47) 66workaround_reset_end cortex_x4, ERRATUM(2763018) 67 68check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1) 69 70workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013 71 mrs x1, id_aa64pfr1_el1 72 ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 73 cbz x2, #1f 74 sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14) 751: 76workaround_reset_end cortex_x4, ERRATUM(2816013) 77 78check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1) 79 80workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503 81 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8) 82workaround_reset_end cortex_x4, ERRATUM(2897503) 83 84check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1) 85 86workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985 87 sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10)) 88workaround_reset_end cortex_x4, ERRATUM(2923985) 89 90check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1) 91 92workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789 93 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14) 94 sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13) 95 sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52) 96workaround_reset_end cortex_x4, ERRATUM(3076789) 97 98check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1) 99 100workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 101#if IMAGE_BL31 102 /* 103 * The Cortex X4 generic vectors are overridden to apply errata 104 * mitigation on exception entry from lower ELs. 105 */ 106 override_vector_table wa_cve_vbar_cortex_x4 107#endif /* IMAGE_BL31 */ 108workaround_reset_end cortex_x4, CVE(2022, 23960) 109 110check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 111 112workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 113 /* --------------------------------- 114 * Sets BIT41 of CPUACTLR6_EL1 which 115 * disables L1 Data cache prefetcher 116 * --------------------------------- 117 */ 118 sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41) 119workaround_reset_end cortex_x4, CVE(2024, 7881) 120 121check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 122 123add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758, NO_APPLY_AT_RESET 124 125check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3) 126 127cpu_reset_func_start cortex_x4 128 /* Disable speculative loads */ 129 msr SSBS, xzr 130cpu_reset_func_end cortex_x4 131 132 /* ---------------------------------------------------- 133 * HW will do the cache maintenance while powering down 134 * ---------------------------------------------------- 135 */ 136func cortex_x4_core_pwr_dwn 137 /* --------------------------------------------------- 138 * Enable CPU power down bit in power control register 139 * --------------------------------------------------- 140 */ 141 sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 142 143 apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV 144 145 isb 146 ret 147endfunc cortex_x4_core_pwr_dwn 148 149 /* --------------------------------------------- 150 * This function provides Cortex X4-specific 151 * register information for crash reporting. 152 * It needs to return with x6 pointing to 153 * a list of register names in ascii and 154 * x8 - x15 having values of registers to be 155 * reported. 156 * --------------------------------------------- 157 */ 158.section .rodata.cortex_x4_regs, "aS" 159cortex_x4_regs: /* The ascii list of register names to be reported */ 160 .asciz "cpuectlr_el1", "" 161 162func cortex_x4_cpu_reg_dump 163 adr x6, cortex_x4_regs 164 mrs x8, CORTEX_X4_CPUECTLR_EL1 165 ret 166endfunc cortex_x4_cpu_reg_dump 167 168declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \ 169 cortex_x4_reset_func, \ 170 CPU_NO_EXTRA1_FUNC, \ 171 CPU_NO_EXTRA2_FUNC, \ 172 CPU_NO_EXTRA3_FUNC, \ 173 check_erratum_cortex_x4_7881, \ 174 cortex_x4_core_pwr_dwn 175