1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 30 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 31workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 32 33check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 34 35workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 36 /* Disable retention control for WFI and WFE. */ 37 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 38 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 39 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 40 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 41workaround_reset_end cortex_x3, ERRATUM(2615812) 42 43check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 44 45workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 46#if IMAGE_BL31 47 override_vector_table wa_cve_vbar_cortex_x3 48#endif /* IMAGE_BL31 */ 49workaround_reset_end cortex_x3, CVE(2022, 23960) 50 51check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 52 53cpu_reset_func_start cortex_x3 54 /* Disable speculative loads */ 55 msr SSBS, xzr 56cpu_reset_func_end cortex_x3 57 58 /* ---------------------------------------------------- 59 * HW will do the cache maintenance while powering down 60 * ---------------------------------------------------- 61 */ 62func cortex_x3_core_pwr_dwn 63apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 64 /* --------------------------------------------------- 65 * Enable CPU power down bit in power control register 66 * --------------------------------------------------- 67 */ 68 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 69 isb 70 ret 71endfunc cortex_x3_core_pwr_dwn 72 73errata_report_shim cortex_x3 74 75 /* --------------------------------------------- 76 * This function provides Cortex-X3- 77 * specific register information for crash 78 * reporting. It needs to return with x6 79 * pointing to a list of register names in ascii 80 * and x8 - x15 having values of registers to be 81 * reported. 82 * --------------------------------------------- 83 */ 84.section .rodata.cortex_x3_regs, "aS" 85cortex_x3_regs: /* The ascii list of register names to be reported */ 86 .asciz "cpuectlr_el1", "" 87 88func cortex_x3_cpu_reg_dump 89 adr x6, cortex_x3_regs 90 mrs x8, CORTEX_X3_CPUECTLR_EL1 91 ret 92endfunc cortex_x3_cpu_reg_dump 93 94declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ 95 cortex_x3_reset_func, \ 96 cortex_x3_core_pwr_dwn 97