1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 30workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31 sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46) 32workaround_reset_end cortex_x3, CVE(2024, 5660) 33 34check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2) 35 36workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 37 sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 38 CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH 39workaround_reset_end cortex_x3, ERRATUM(2070301) 40 41check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) 42 43workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875 44 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) 45workaround_reset_end cortex_x3, ERRATUM(2266875) 46 47check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0) 48 49workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506 50 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) 51workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB 52 53check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1) 54 55workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 56 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 57 * the workaround. Second call clears it to undo it. */ 58 sysreg_bit_toggle CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 59workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 60 61check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 62 63workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204 64 /* Set bit 40 in CPUACTLR2_EL1 */ 65 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40) 66workaround_reset_end cortex_x3, ERRATUM(2372204) 67 68check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0) 69 70workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 71 /* Disable retention control for WFI and WFE. */ 72 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 73 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 74 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 75 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 76workaround_reset_end cortex_x3, ERRATUM(2615812) 77 78check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 79 80workaround_runtime_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945 81 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 82workaround_runtime_end cortex_x3, ERRATUM(2641945), NO_ISB 83 84check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0) 85 86workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 87 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 88 sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 89 sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 90workaround_reset_end cortex_x3, ERRATUM(2742421) 91 92check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) 93 94workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088 95 /* dsb before isb of power down sequence */ 96 dsb sy 97workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB 98 99check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1) 100 101workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509 102 /* Set CPUACTLR3_EL1 bit 47 */ 103 sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 104workaround_reset_end cortex_x3, ERRATUM(2779509) 105 106check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1) 107 108workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 109#if IMAGE_BL31 110 override_vector_table wa_cve_vbar_cortex_x3 111#endif /* IMAGE_BL31 */ 112workaround_reset_end cortex_x3, CVE(2022, 23960) 113 114check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 115 116workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 117 /* --------------------------------- 118 * Sets BIT41 of CPUACTLR6_EL1 which 119 * disables L1 Data cache prefetcher 120 * --------------------------------- 121 */ 122 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 123workaround_reset_end cortex_x3, CVE(2024, 7881) 124 125check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 126 127cpu_reset_func_start cortex_x3 128 /* Disable speculative loads */ 129 msr SSBS, xzr 130cpu_reset_func_end cortex_x3 131 132 /* ---------------------------------------------------- 133 * HW will do the cache maintenance while powering down 134 * ---------------------------------------------------- 135 */ 136func cortex_x3_core_pwr_dwn 137 apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV 138 /* --------------------------------------------------- 139 * Enable CPU power down bit in power control register 140 * --------------------------------------------------- 141 */ 142 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 143 apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV 144 isb 145 ret 146endfunc cortex_x3_core_pwr_dwn 147 148 /* --------------------------------------------- 149 * This function provides Cortex-X3- 150 * specific register information for crash 151 * reporting. It needs to return with x6 152 * pointing to a list of register names in ascii 153 * and x8 - x15 having values of registers to be 154 * reported. 155 * --------------------------------------------- 156 */ 157.section .rodata.cortex_x3_regs, "aS" 158cortex_x3_regs: /* The ascii list of register names to be reported */ 159 .asciz "cpuectlr_el1", "" 160 161func cortex_x3_cpu_reg_dump 162 adr x6, cortex_x3_regs 163 mrs x8, CORTEX_X3_CPUECTLR_EL1 164 ret 165endfunc cortex_x3_cpu_reg_dump 166 167declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \ 168 cortex_x3_reset_func, \ 169 CPU_NO_EXTRA1_FUNC, \ 170 CPU_NO_EXTRA2_FUNC, \ 171 CPU_NO_EXTRA3_FUNC, \ 172 check_erratum_cortex_x3_7881, \ 173 cortex_x3_core_pwr_dwn 174