1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_x3_3701769 26 27add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769, NO_APPLY_AT_RESET 28 29check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2) 30 31#if WORKAROUND_CVE_2022_23960 32 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 33#endif /* WORKAROUND_CVE_2022_23960 */ 34 35/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 36workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 37 sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46) 38workaround_reset_end cortex_x3, CVE(2024, 5660) 39 40check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2) 41 42workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 43 sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 44 CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH 45workaround_reset_end cortex_x3, ERRATUM(2070301) 46 47check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) 48 49workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875 50 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) 51workaround_reset_end cortex_x3, ERRATUM(2266875) 52 53check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0) 54 55workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506 56 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) 57workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB 58 59check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1) 60 61workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 62 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 63workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 64 65check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 66 67workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204 68 /* Set bit 40 in CPUACTLR2_EL1 */ 69 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40) 70workaround_reset_end cortex_x3, ERRATUM(2372204) 71 72check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0) 73 74workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 75 /* Disable retention control for WFI and WFE. */ 76 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 77 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 78 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 79 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 80workaround_reset_end cortex_x3, ERRATUM(2615812) 81 82check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 83 84workaround_runtime_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945 85 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 86workaround_runtime_end cortex_x3, ERRATUM(2641945), NO_ISB 87 88check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0) 89 90workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 91 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 92 sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 93 sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 94workaround_reset_end cortex_x3, ERRATUM(2742421) 95 96check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) 97 98workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088 99 /* dsb before isb of power down sequence */ 100 dsb sy 101workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB 102 103check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1) 104 105workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509 106 /* Set CPUACTLR3_EL1 bit 47 */ 107 sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 108workaround_reset_end cortex_x3, ERRATUM(2779509) 109 110check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1) 111 112workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 113#if IMAGE_BL31 114 override_vector_table wa_cve_vbar_cortex_x3 115#endif /* IMAGE_BL31 */ 116workaround_reset_end cortex_x3, CVE(2022, 23960) 117 118check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 119 120workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 121 /* --------------------------------- 122 * Sets BIT41 of CPUACTLR6_EL1 which 123 * disables L1 Data cache prefetcher 124 * --------------------------------- 125 */ 126 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 127workaround_reset_end cortex_x3, CVE(2024, 7881) 128 129check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 130 131cpu_reset_func_start cortex_x3 132 /* Disable speculative loads */ 133 msr SSBS, xzr 134cpu_reset_func_end cortex_x3 135 136 /* ---------------------------------------------------- 137 * HW will do the cache maintenance while powering down 138 * ---------------------------------------------------- 139 */ 140func cortex_x3_core_pwr_dwn 141 apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV 142 /* --------------------------------------------------- 143 * Enable CPU power down bit in power control register 144 * --------------------------------------------------- 145 */ 146 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 147 apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV 148 isb 149 ret 150endfunc cortex_x3_core_pwr_dwn 151 152 /* --------------------------------------------- 153 * This function provides Cortex-X3- 154 * specific register information for crash 155 * reporting. It needs to return with x6 156 * pointing to a list of register names in ascii 157 * and x8 - x15 having values of registers to be 158 * reported. 159 * --------------------------------------------- 160 */ 161.section .rodata.cortex_x3_regs, "aS" 162cortex_x3_regs: /* The ascii list of register names to be reported */ 163 .asciz "cpuectlr_el1", "" 164 165func cortex_x3_cpu_reg_dump 166 adr x6, cortex_x3_regs 167 mrs x8, CORTEX_X3_CPUECTLR_EL1 168 ret 169endfunc cortex_x3_cpu_reg_dump 170 171declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \ 172 cortex_x3_reset_func, \ 173 CPU_NO_EXTRA1_FUNC, \ 174 CPU_NO_EXTRA2_FUNC, \ 175 CPU_NO_EXTRA3_FUNC, \ 176 check_erratum_cortex_x3_7881, \ 177 cortex_x3_core_pwr_dwn 178