1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_x3_3701769 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31cpu_reset_prologue cortex_x3 32 33workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875 34 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) 35workaround_reset_end cortex_x3, ERRATUM(2266875) 36 37check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0) 38 39workaround_reset_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506 40 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) 41workaround_reset_end cortex_x3, ERRATUM(2302506) 42 43check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1) 44 45.global erratum_cortex_x3_2313909_wa 46workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 47 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 48 * the workaround. Second call clears it to undo it. */ 49 sysreg_bit_toggle CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 50workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 51 52check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 53 54workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204 55 /* Set bit 40 in CPUACTLR2_EL1 */ 56 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40) 57workaround_reset_end cortex_x3, ERRATUM(2372204) 58 59check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0) 60 61workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 62 /* Disable retention control for WFI and WFE. */ 63 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 64 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 65 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 66 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 67workaround_reset_end cortex_x3, ERRATUM(2615812) 68 69check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 70 71workaround_reset_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945 72 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 73workaround_reset_end cortex_x3, ERRATUM(2641945) 74 75check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0) 76 77workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 78 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 79 sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 80 sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 81workaround_reset_end cortex_x3, ERRATUM(2742421) 82 83check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) 84 85workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088 86 /* dsb before isb of power down sequence */ 87 dsb sy 88workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB 89 90check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1) 91 92workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509 93 /* Set CPUACTLR3_EL1 bit 47 */ 94 sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 95workaround_reset_end cortex_x3, ERRATUM(2779509) 96 97check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1) 98 99workaround_reset_start cortex_x3, ERRATUM(3213672), ERRATA_X3_3213672 100 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(36) 101workaround_reset_end cortex_x3, ERRATUM(3213672) 102 103check_erratum_ls cortex_x3, ERRATUM(3213672), CPU_REV(1, 2) 104 105workaround_reset_start cortex_x3, ERRATUM(3692984), ERRATA_X3_3692984 106 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 107workaround_reset_end cortex_x3, ERRATUM(3692984) 108 109check_erratum_ls cortex_x3, ERRATUM(3692984), CPU_REV(1, 2) 110 111add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769 112 113check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2) 114 115workaround_reset_start cortex_x3, ERRATUM(3827463), ERRATA_X3_3827463 116 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(1) 117workaround_reset_end cortex_x3, ERRATUM(3827463) 118 119check_erratum_ls cortex_x3, ERRATUM(3827463), CPU_REV(1, 1) 120 121workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 122#if IMAGE_BL31 123 override_vector_table wa_cve_vbar_cortex_x3 124#endif /* IMAGE_BL31 */ 125workaround_reset_end cortex_x3, CVE(2022, 23960) 126 127check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 128 129/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 130workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 131 sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46) 132workaround_reset_end cortex_x3, CVE(2024, 5660) 133 134check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2) 135 136workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 137 /* --------------------------------- 138 * Sets BIT41 of CPUACTLR6_EL1 which 139 * disables L1 Data cache prefetcher 140 * --------------------------------- 141 */ 142 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 143workaround_reset_end cortex_x3, CVE(2024, 7881) 144 145check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 146 147cpu_reset_func_start cortex_x3 148 /* Disable speculative loads */ 149 msr SSBS, xzr 150 enable_mpmm 151cpu_reset_func_end cortex_x3 152 153 /* ---------------------------------------------------- 154 * HW will do the cache maintenance while powering down 155 * ---------------------------------------------------- 156 */ 157func cortex_x3_core_pwr_dwn 158 apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 159 /* --------------------------------------------------- 160 * Enable CPU power down bit in power control register 161 * --------------------------------------------------- 162 */ 163 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 164 apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV 165 isb 166 ret 167endfunc cortex_x3_core_pwr_dwn 168 169 /* --------------------------------------------- 170 * This function provides Cortex-X3- 171 * specific register information for crash 172 * reporting. It needs to return with x6 173 * pointing to a list of register names in ascii 174 * and x8 - x15 having values of registers to be 175 * reported. 176 * --------------------------------------------- 177 */ 178.section .rodata.cortex_x3_regs, "aS" 179cortex_x3_regs: /* The ascii list of register names to be reported */ 180 .asciz "cpuectlr_el1", "" 181 182func cortex_x3_cpu_reg_dump 183 adr x6, cortex_x3_regs 184 mrs x8, CORTEX_X3_CPUECTLR_EL1 185 ret 186endfunc cortex_x3_cpu_reg_dump 187 188declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ 189 cortex_x3_reset_func, \ 190 cortex_x3_core_pwr_dwn 191