1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 30workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31 sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46) 32workaround_reset_end cortex_x3, CVE(2024, 5660) 33 34check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2) 35 36workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 37 sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 38 CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH 39workaround_reset_end cortex_x3, ERRATUM(2070301) 40 41check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) 42 43workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875 44 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) 45workaround_reset_end cortex_x3, ERRATUM(2266875) 46 47check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0) 48 49workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506 50 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) 51workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB 52 53check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1) 54 55workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 56 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 57workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 58 59check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 60 61workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204 62 /* Set bit 40 in CPUACTLR2_EL1 */ 63 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40) 64workaround_reset_end cortex_x3, ERRATUM(2372204) 65 66check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0) 67 68workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 69 /* Disable retention control for WFI and WFE. */ 70 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 71 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 72 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 73 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 74workaround_reset_end cortex_x3, ERRATUM(2615812) 75 76check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 77 78workaround_runtime_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945 79 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 80workaround_runtime_end cortex_x3, ERRATUM(2641945), NO_ISB 81 82check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0) 83 84workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 85 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 86 sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 87 sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 88workaround_reset_end cortex_x3, ERRATUM(2742421) 89 90check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) 91 92workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088 93 /* dsb before isb of power down sequence */ 94 dsb sy 95workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB 96 97check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1) 98 99workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509 100 /* Set CPUACTLR3_EL1 bit 47 */ 101 sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 102workaround_reset_end cortex_x3, ERRATUM(2779509) 103 104check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1) 105 106workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 107#if IMAGE_BL31 108 override_vector_table wa_cve_vbar_cortex_x3 109#endif /* IMAGE_BL31 */ 110workaround_reset_end cortex_x3, CVE(2022, 23960) 111 112check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 113 114cpu_reset_func_start cortex_x3 115 /* Disable speculative loads */ 116 msr SSBS, xzr 117cpu_reset_func_end cortex_x3 118 119 /* ---------------------------------------------------- 120 * HW will do the cache maintenance while powering down 121 * ---------------------------------------------------- 122 */ 123func cortex_x3_core_pwr_dwn 124 apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV 125 /* --------------------------------------------------- 126 * Enable CPU power down bit in power control register 127 * --------------------------------------------------- 128 */ 129 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 130 apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV 131 isb 132 ret 133endfunc cortex_x3_core_pwr_dwn 134 135 /* --------------------------------------------- 136 * This function provides Cortex-X3- 137 * specific register information for crash 138 * reporting. It needs to return with x6 139 * pointing to a list of register names in ascii 140 * and x8 - x15 having values of registers to be 141 * reported. 142 * --------------------------------------------- 143 */ 144.section .rodata.cortex_x3_regs, "aS" 145cortex_x3_regs: /* The ascii list of register names to be reported */ 146 .asciz "cpuectlr_el1", "" 147 148func cortex_x3_cpu_reg_dump 149 adr x6, cortex_x3_regs 150 mrs x8, CORTEX_X3_CPUECTLR_EL1 151 ret 152endfunc cortex_x3_cpu_reg_dump 153 154declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ 155 cortex_x3_reset_func, \ 156 cortex_x3_core_pwr_dwn 157