1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 30 ldr x0, =0x6 31 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 32 ldr x0, =0xF3A08002 33 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 34 ldr x0, =0xFFF0F7FE 35 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 36 ldr x0, =0x40000001003ff 37 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 38workaround_reset_end cortex_x2, ERRATUM(2002765) 39 40check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 41 42workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 43 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 44workaround_reset_end cortex_x2, ERRATUM(2017096) 45 46check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 47 48workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056 49 sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 50 CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 51workaround_reset_end cortex_x2, ERRATUM(2058056) 52 53check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1) 54 55workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 56 /* Apply instruction patching sequence */ 57 ldr x0, =0x3 58 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 59 ldr x0, =0xF3A08002 60 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 61 ldr x0, =0xFFF0F7FE 62 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 63 ldr x0, =0x10002001003FF 64 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 65 ldr x0, =0x4 66 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 67 ldr x0, =0xBF200000 68 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 69 ldr x0, =0xFFEF0000 70 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 71 ldr x0, =0x10002001003F3 72 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 73workaround_reset_end cortex_x2, ERRATUM(2081180) 74 75check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 76 77workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 78 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 79 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 80workaround_reset_end cortex_x2, ERRATUM(2083908) 81 82check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 83 84workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 85 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 86 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 87workaround_reset_end cortex_x2, ERRATUM(2147715) 88 89check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 90 91workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 92 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 93 94 /* Apply instruction patching sequence */ 95 ldr x0, =0x5 96 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 97 ldr x0, =0x10F600E000 98 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 99 ldr x0, =0x10FF80E000 100 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 101 ldr x0, =0x80000000003FF 102 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 103workaround_reset_end cortex_x2, ERRATUM(2216384) 104 105check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 106 107workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 108 /* Apply the workaround */ 109 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 110workaround_reset_end cortex_x2, ERRATUM(2282622) 111 112check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 113 114workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 115 /* Set bit 40 in CPUACTLR2_EL1 */ 116 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 117workaround_reset_end cortex_x2, ERRATUM(2371105) 118 119check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 120 121workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 122 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 123 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 124 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 125workaround_reset_end cortex_x2, ERRATUM(2742423) 126 127check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 128 129workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 130 /* dsb before isb of power down sequence */ 131 dsb sy 132workaround_reset_end cortex_x2, ERRATUM(2768515) 133 134check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 135 136workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 137#if IMAGE_BL31 138 /* 139 * The Cortex-X2 generic vectors are overridden to apply errata 140 * mitigation on exception entry from lower ELs. 141 */ 142 override_vector_table wa_cve_vbar_cortex_x2 143#endif /* IMAGE_BL31 */ 144workaround_reset_end cortex_x2, CVE(2022, 23960) 145 146check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 147 148/* 149 * ERRATA_DSU_2313941 : 150 * The errata is defined in dsu_helpers.S but applies to cortex_x2 151 * as well. Henceforth creating symbolic names to the already existing errata 152 * workaround functions to get them registered under the Errata Framework. 153 */ 154.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941 155.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa 156add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 157 158 /* ---------------------------------------------------- 159 * HW will do the cache maintenance while powering down 160 * ---------------------------------------------------- 161 */ 162func cortex_x2_core_pwr_dwn 163 /* --------------------------------------------------- 164 * Enable CPU power down bit in power control register 165 * --------------------------------------------------- 166 */ 167 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 168 169#if ERRATA_X2_2768515 170 mov x15, x30 171 bl cpu_get_rev_var 172 bl erratum_cortex_x2_2768515_wa 173 mov x30, x15 174#endif /* ERRATA_X2_2768515 */ 175 isb 176 ret 177endfunc cortex_x2_core_pwr_dwn 178 179errata_report_shim cortex_x2 180 181cpu_reset_func_start cortex_x2 182 /* Disable speculative loads */ 183 msr SSBS, xzr 184cpu_reset_func_end cortex_x2 185 186 /* --------------------------------------------- 187 * This function provides Cortex X2 specific 188 * register information for crash reporting. 189 * It needs to return with x6 pointing to 190 * a list of register names in ascii and 191 * x8 - x15 having values of registers to be 192 * reported. 193 * --------------------------------------------- 194 */ 195.section .rodata.cortex_x2_regs, "aS" 196cortex_x2_regs: /* The ascii list of register names to be reported */ 197 .asciz "cpuectlr_el1", "" 198 199func cortex_x2_cpu_reg_dump 200 adr x6, cortex_x2_regs 201 mrs x8, CORTEX_X2_CPUECTLR_EL1 202 ret 203endfunc cortex_x2_cpu_reg_dump 204 205declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 206 cortex_x2_reset_func, \ 207 cortex_x2_core_pwr_dwn 208