1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_x2_3701772 26 27add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772, NO_APPLY_AT_RESET 28 29check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1) 30 31#if WORKAROUND_CVE_2022_23960 32 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 33#endif /* WORKAROUND_CVE_2022_23960 */ 34 35/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 36workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 37 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46) 38workaround_reset_end cortex_x2, CVE(2024, 5660) 39 40check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1) 41 42workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 43 ldr x0, =0x6 44 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 45 ldr x0, =0xF3A08002 46 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 47 ldr x0, =0xFFF0F7FE 48 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 49 ldr x0, =0x40000001003ff 50 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 51workaround_reset_end cortex_x2, ERRATUM(2002765) 52 53check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 54 55workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 56 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 57workaround_reset_end cortex_x2, ERRATUM(2017096) 58 59check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 60 61workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056 62 sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 63 CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 64workaround_reset_end cortex_x2, ERRATUM(2058056) 65 66check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1) 67 68workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 69 /* Apply instruction patching sequence */ 70 ldr x0, =0x3 71 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 72 ldr x0, =0xF3A08002 73 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 74 ldr x0, =0xFFF0F7FE 75 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 76 ldr x0, =0x10002001003FF 77 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 78 ldr x0, =0x4 79 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 80 ldr x0, =0xBF200000 81 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 82 ldr x0, =0xFFEF0000 83 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 84 ldr x0, =0x10002001003F3 85 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 86workaround_reset_end cortex_x2, ERRATUM(2081180) 87 88check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 89 90workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 91 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 92 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 93workaround_reset_end cortex_x2, ERRATUM(2083908) 94 95check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 96 97workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 98 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 99 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 100workaround_reset_end cortex_x2, ERRATUM(2147715) 101 102check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 103 104workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 105 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 106 107 /* Apply instruction patching sequence */ 108 ldr x0, =0x5 109 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 110 ldr x0, =0x10F600E000 111 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 112 ldr x0, =0x10FF80E000 113 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 114 ldr x0, =0x80000000003FF 115 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 116workaround_reset_end cortex_x2, ERRATUM(2216384) 117 118check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 119 120workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 121 /* Apply the workaround */ 122 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 123workaround_reset_end cortex_x2, ERRATUM(2282622) 124 125check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 126 127workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 128 /* Set bit 40 in CPUACTLR2_EL1 */ 129 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 130workaround_reset_end cortex_x2, ERRATUM(2371105) 131 132check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 133 134workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 135 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 136 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 137 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 138workaround_reset_end cortex_x2, ERRATUM(2742423) 139 140check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 141 142workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 143 /* dsb before isb of power down sequence */ 144 dsb sy 145workaround_runtime_end cortex_x2, ERRATUM(2768515) 146 147check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 148 149workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471 150 sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47) 151workaround_reset_end cortex_x2, ERRATUM(2778471) 152 153check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1) 154 155workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 156#if IMAGE_BL31 157 /* 158 * The Cortex-X2 generic vectors are overridden to apply errata 159 * mitigation on exception entry from lower ELs. 160 */ 161 override_vector_table wa_cve_vbar_cortex_x2 162#endif /* IMAGE_BL31 */ 163workaround_reset_end cortex_x2, CVE(2022, 23960) 164 165check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 166 167/* 168 * ERRATA_DSU_2313941 : 169 * The errata is defined in dsu_helpers.S but applies to cortex_x2 170 * as well. Henceforth creating symbolic names to the already existing errata 171 * workaround functions to get them registered under the Errata Framework. 172 */ 173.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941 174.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa 175add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 176 177 /* ---------------------------------------------------- 178 * HW will do the cache maintenance while powering down 179 * ---------------------------------------------------- 180 */ 181func cortex_x2_core_pwr_dwn 182 /* --------------------------------------------------- 183 * Enable CPU power down bit in power control register 184 * --------------------------------------------------- 185 */ 186 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 187 188 apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV 189 isb 190 ret 191endfunc cortex_x2_core_pwr_dwn 192 193cpu_reset_func_start cortex_x2 194 /* Disable speculative loads */ 195 msr SSBS, xzr 196cpu_reset_func_end cortex_x2 197 198 /* --------------------------------------------- 199 * This function provides Cortex X2 specific 200 * register information for crash reporting. 201 * It needs to return with x6 pointing to 202 * a list of register names in ascii and 203 * x8 - x15 having values of registers to be 204 * reported. 205 * --------------------------------------------- 206 */ 207.section .rodata.cortex_x2_regs, "aS" 208cortex_x2_regs: /* The ascii list of register names to be reported */ 209 .asciz "cpuectlr_el1", "" 210 211func cortex_x2_cpu_reg_dump 212 adr x6, cortex_x2_regs 213 mrs x8, CORTEX_X2_CPUECTLR_EL1 214 ret 215endfunc cortex_x2_cpu_reg_dump 216 217declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 218 cortex_x2_reset_func, \ 219 cortex_x2_core_pwr_dwn 220