1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 30 ldr x0, =0x6 31 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 32 ldr x0, =0xF3A08002 33 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 34 ldr x0, =0xFFF0F7FE 35 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 36 ldr x0, =0x40000001003ff 37 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 38workaround_reset_end cortex_x2, ERRATUM(2002765) 39 40check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 41 42workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 43 mrs x1, CORTEX_X2_CPUECTLR_EL1 44 orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 45 msr CORTEX_X2_CPUECTLR_EL1, x1 46workaround_reset_end cortex_x2, ERRATUM(2017096) 47 48check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 49 50workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056 51 mrs x1, CORTEX_X2_CPUECTLR2_EL1 52 mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV 53 bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 54 msr CORTEX_X2_CPUECTLR2_EL1, x1 55workaround_reset_end cortex_x2, ERRATUM(2058056) 56 57check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 0) 58 59workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 60 /* Apply instruction patching sequence */ 61 ldr x0, =0x3 62 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 63 ldr x0, =0xF3A08002 64 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 65 ldr x0, =0xFFF0F7FE 66 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 67 ldr x0, =0x10002001003FF 68 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 69 ldr x0, =0x4 70 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 71 ldr x0, =0xBF200000 72 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 73 ldr x0, =0xFFEF0000 74 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 75 ldr x0, =0x10002001003F3 76 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 77workaround_reset_end cortex_x2, ERRATUM(2081180) 78 79check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 80 81workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 82 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 83 mrs x1, CORTEX_X2_CPUACTLR5_EL1 84 orr x1, x1, #BIT(13) 85 msr CORTEX_X2_CPUACTLR5_EL1, x1 86workaround_reset_end cortex_x2, ERRATUM(2083908) 87 88check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 89 90workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 91 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 92 mrs x1, CORTEX_X2_CPUACTLR_EL1 93 orr x1, x1, CORTEX_X2_CPUACTLR_EL1_BIT_22 94 msr CORTEX_X2_CPUACTLR_EL1, x1 95workaround_reset_end cortex_x2, ERRATUM(2147715) 96 97check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 98 99workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 100 mrs x1, CORTEX_X2_CPUACTLR5_EL1 101 orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 102 msr CORTEX_X2_CPUACTLR5_EL1, x1 103 104 /* Apply instruction patching sequence */ 105 ldr x0, =0x5 106 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 107 ldr x0, =0x10F600E000 108 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 109 ldr x0, =0x10FF80E000 110 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 111 ldr x0, =0x80000000003FF 112 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 113workaround_reset_end cortex_x2, ERRATUM(2216384) 114 115check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 116 117workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 118 /* Apply the workaround */ 119 mrs x1, CORTEX_X2_CPUACTLR2_EL1 120 orr x1, x1, #BIT(0) 121 msr CORTEX_X2_CPUACTLR2_EL1, x1 122workaround_reset_end cortex_x2, ERRATUM(2282622) 123 124check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 125 126workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 127 /* Set bit 40 in CPUACTLR2_EL1 */ 128 mrs x1, CORTEX_X2_CPUACTLR2_EL1 129 orr x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40 130 msr CORTEX_X2_CPUACTLR2_EL1, x1 131workaround_reset_end cortex_x2, ERRATUM(2371105) 132 133check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 134 135workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 136 /* dsb before isb of power down sequence */ 137 dsb sy 138workaround_reset_end cortex_x2, ERRATUM(2768515) 139 140check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 141 142workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 143#if IMAGE_BL31 144 /* 145 * The Cortex-X2 generic vectors are overridden to apply errata 146 * mitigation on exception entry from lower ELs. 147 */ 148 adr x0, wa_cve_vbar_cortex_x2 149 msr vbar_el3, x0 150#endif /* IMAGE_BL31 */ 151workaround_reset_end cortex_x2, CVE(2022, 23960) 152 153check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 154 155/* 156 * ERRATA_DSU_2313941 : 157 * The errata is defined in dsu_helpers.S but applies to cortex_x2 158 * as well. Henceforth creating symbolic names to the already existing errata 159 * workaround functions to get them registered under the Errata Framework. 160 */ 161.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941 162.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa 163add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 164 165 /* ---------------------------------------------------- 166 * HW will do the cache maintenance while powering down 167 * ---------------------------------------------------- 168 */ 169func cortex_x2_core_pwr_dwn 170 /* --------------------------------------------------- 171 * Enable CPU power down bit in power control register 172 * --------------------------------------------------- 173 */ 174 mrs x0, CORTEX_X2_CPUPWRCTLR_EL1 175 orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 176 msr CORTEX_X2_CPUPWRCTLR_EL1, x0 177#if ERRATA_X2_2768515 178 mov x15, x30 179 bl cpu_get_rev_var 180 bl erratum_cortex_x2_2768515_wa 181 mov x30, x15 182#endif /* ERRATA_X2_2768515 */ 183 isb 184 ret 185endfunc cortex_x2_core_pwr_dwn 186 187errata_report_shim cortex_x2 188 189cpu_reset_func_start cortex_x2 190 /* Disable speculative loads */ 191 msr SSBS, xzr 192cpu_reset_func_end cortex_x2 193 194 /* --------------------------------------------- 195 * This function provides Cortex X2 specific 196 * register information for crash reporting. 197 * It needs to return with x6 pointing to 198 * a list of register names in ascii and 199 * x8 - x15 having values of registers to be 200 * reported. 201 * --------------------------------------------- 202 */ 203.section .rodata.cortex_x2_regs, "aS" 204cortex_x2_regs: /* The ascii list of register names to be reported */ 205 .asciz "cpuectlr_el1", "" 206 207func cortex_x2_cpu_reg_dump 208 adr x6, cortex_x2_regs 209 mrs x8, CORTEX_X2_CPUECTLR_EL1 210 ret 211endfunc cortex_x2_cpu_reg_dump 212 213declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 214 cortex_x2_reset_func, \ 215 cortex_x2_core_pwr_dwn 216