1/* 2 * Copyright (c) 2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Cortex X2 Errata #2002765. 26 * This applies to revisions r0p0, r1p0, and r2p0 and 27 * is open. 28 * x0: variant[4:7] and revision[0:3] of current cpu. 29 * Shall clobber: x0, x1, x17 30 * -------------------------------------------------- 31 */ 32func errata_cortex_x2_2002765_wa 33 /* Check workaround compatibility. */ 34 mov x17, x30 35 bl check_errata_2002765 36 cbz x0, 1f 37 38 ldr x0, =0x6 39 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 40 ldr x0, =0xF3A08002 41 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 42 ldr x0, =0xFFF0F7FE 43 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 44 ldr x0, =0x40000001003ff 45 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 46 isb 47 481: 49 ret x17 50endfunc errata_cortex_x2_2002765_wa 51 52func check_errata_2002765 53 /* Applies to r0p0 - r2p0 */ 54 mov x1, #0x20 55 b cpu_rev_var_ls 56endfunc check_errata_2002765 57 58 /* -------------------------------------------------- 59 * Errata Workaround for Cortex X2 Errata #2058056. 60 * This applies to revisions r0p0, r1p0, and r2p0 and 61 * is open. 62 * x0: variant[4:7] and revision[0:3] of current cpu. 63 * Shall clobber: x0, x1, x17 64 * -------------------------------------------------- 65 */ 66func errata_cortex_x2_2058056_wa 67 /* Check workaround compatibility. */ 68 mov x17, x30 69 bl check_errata_2058056 70 cbz x0, 1f 71 72 mrs x1, CORTEX_X2_CPUECTLR2_EL1 73 mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV 74 bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 75 msr CORTEX_X2_CPUECTLR2_EL1, x1 76 771: 78 ret x17 79endfunc errata_cortex_x2_2058056_wa 80 81func check_errata_2058056 82 /* Applies to r0p0 - r2p0 */ 83 mov x1, #0x20 84 b cpu_rev_var_ls 85endfunc check_errata_2058056 86 87 /* -------------------------------------------------- 88 * Errata Workaround for Cortex X2 Errata #2083908. 89 * This applies to revision r2p0 and is open. 90 * x0: variant[4:7] and revision[0:3] of current cpu. 91 * Shall clobber: x0-x2, x17 92 * -------------------------------------------------- 93 */ 94func errata_cortex_x2_2083908_wa 95 /* Check workaround compatibility. */ 96 mov x17, x30 97 bl check_errata_2083908 98 cbz x0, 1f 99 100 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 101 mrs x1, CORTEX_X2_CPUACTLR5_EL1 102 orr x1, x1, #BIT(13) 103 msr CORTEX_X2_CPUACTLR5_EL1, x1 104 1051: 106 ret x17 107endfunc errata_cortex_x2_2083908_wa 108 109func check_errata_2083908 110 /* Applies to r2p0 */ 111 mov x1, #0x20 112 mov x2, #0x20 113 b cpu_rev_var_range 114endfunc check_errata_2083908 115 116 /* ---------------------------------------------------- 117 * HW will do the cache maintenance while powering down 118 * ---------------------------------------------------- 119 */ 120func cortex_x2_core_pwr_dwn 121 /* --------------------------------------------------- 122 * Enable CPU power down bit in power control register 123 * --------------------------------------------------- 124 */ 125 mrs x0, CORTEX_X2_CPUPWRCTLR_EL1 126 orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 127 msr CORTEX_X2_CPUPWRCTLR_EL1, x0 128 isb 129 ret 130endfunc cortex_x2_core_pwr_dwn 131 132 /* 133 * Errata printing function for Cortex X2. Must follow AAPCS. 134 */ 135#if REPORT_ERRATA 136func cortex_x2_errata_report 137 stp x8, x30, [sp, #-16]! 138 139 bl cpu_get_rev_var 140 mov x8, x0 141 142 /* 143 * Report all errata. The revision-variant information is passed to 144 * checking functions of each errata. 145 */ 146 report_errata ERRATA_X2_2002765, cortex_x2, 2002765 147 report_errata ERRATA_X2_2058056, cortex_x2, 2058056 148 report_errata ERRATA_X2_2083908, cortex_x2, 2083908 149 150 ldp x8, x30, [sp], #16 151 ret 152endfunc cortex_x2_errata_report 153#endif 154 155func cortex_x2_reset_func 156 mov x19, x30 157 158 /* Disable speculative loads */ 159 msr SSBS, xzr 160 isb 161 162 /* Get the CPU revision and stash it in x18. */ 163 bl cpu_get_rev_var 164 mov x18, x0 165 166#if ERRATA_X2_2002765 167 mov x0, x18 168 bl errata_cortex_x2_2002765_wa 169#endif 170 171#if ERRATA_X2_2058056 172 mov x0, x18 173 bl errata_cortex_x2_2058056_wa 174#endif 175 176#if ERRATA_X2_2083908 177 mov x0, x18 178 bl errata_cortex_x2_2083908_wa 179#endif 180 181 ret x19 182endfunc cortex_x2_reset_func 183 184 /* --------------------------------------------- 185 * This function provides Cortex X2 specific 186 * register information for crash reporting. 187 * It needs to return with x6 pointing to 188 * a list of register names in ascii and 189 * x8 - x15 having values of registers to be 190 * reported. 191 * --------------------------------------------- 192 */ 193.section .rodata.cortex_x2_regs, "aS" 194cortex_x2_regs: /* The ascii list of register names to be reported */ 195 .asciz "cpuectlr_el1", "" 196 197func cortex_x2_cpu_reg_dump 198 adr x6, cortex_x2_regs 199 mrs x8, CORTEX_X2_CPUECTLR_EL1 200 ret 201endfunc cortex_x2_cpu_reg_dump 202 203declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 204 cortex_x2_reset_func, \ 205 cortex_x2_core_pwr_dwn 206