1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29 /* -------------------------------------------------- 30 * Errata Workaround for Cortex X2 Errata #2002765. 31 * This applies to revisions r0p0, r1p0, and r2p0 and 32 * is open. 33 * x0: variant[4:7] and revision[0:3] of current cpu. 34 * Shall clobber: x0, x1, x17 35 * -------------------------------------------------- 36 */ 37func errata_cortex_x2_2002765_wa 38 /* Check workaround compatibility. */ 39 mov x17, x30 40 bl check_errata_2002765 41 cbz x0, 1f 42 43 ldr x0, =0x6 44 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 45 ldr x0, =0xF3A08002 46 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 47 ldr x0, =0xFFF0F7FE 48 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 49 ldr x0, =0x40000001003ff 50 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 51 isb 52 531: 54 ret x17 55endfunc errata_cortex_x2_2002765_wa 56 57func check_errata_2002765 58 /* Applies to r0p0 - r2p0 */ 59 mov x1, #0x20 60 b cpu_rev_var_ls 61endfunc check_errata_2002765 62 63 /* -------------------------------------------------- 64 * Errata Workaround for Cortex-X2 Errata 2017096. 65 * This applies only to revisions r0p0, r1p0 and r2p0 66 * and is fixed in r2p1. 67 * Inputs: 68 * x0: variant[4:7] and revision[0:3] of current cpu. 69 * Shall clobber: x0, x1, x17 70 * -------------------------------------------------- 71 */ 72func errata_x2_2017096_wa 73 /* Compare x0 against revision r0p0 to r2p0 */ 74 mov x17, x30 75 bl check_errata_2017096 76 cbz x0, 1f 77 mrs x1, CORTEX_X2_CPUECTLR_EL1 78 orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 79 msr CORTEX_X2_CPUECTLR_EL1, x1 80 811: 82 ret x17 83endfunc errata_x2_2017096_wa 84 85func check_errata_2017096 86 /* Applies to r0p0, r1p0, r2p0 */ 87 mov x1, #0x20 88 b cpu_rev_var_ls 89endfunc check_errata_2017096 90 91 /* -------------------------------------------------- 92 * Errata Workaround for Cortex X2 Errata #2058056. 93 * This applies to revisions r0p0, r1p0, and r2p0 and 94 * is open. 95 * x0: variant[4:7] and revision[0:3] of current cpu. 96 * Shall clobber: x0, x1, x17 97 * -------------------------------------------------- 98 */ 99func errata_cortex_x2_2058056_wa 100 /* Check workaround compatibility. */ 101 mov x17, x30 102 bl check_errata_2058056 103 cbz x0, 1f 104 105 mrs x1, CORTEX_X2_CPUECTLR2_EL1 106 mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV 107 bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH 108 msr CORTEX_X2_CPUECTLR2_EL1, x1 109 1101: 111 ret x17 112endfunc errata_cortex_x2_2058056_wa 113 114func check_errata_2058056 115 /* Applies to r0p0 - r2p0 */ 116 mov x1, #0x20 117 b cpu_rev_var_ls 118endfunc check_errata_2058056 119 120 /* -------------------------------------------------- 121 * Errata Workaround for Cortex-X2 Errata 2081180. 122 * This applies to revision r0p0, r1p0 and r2p0 123 * and is fixed in r2p1. 124 * Inputs: 125 * x0: variant[4:7] and revision[0:3] of current cpu. 126 * Shall clobber: x0, x1, x17 127 * -------------------------------------------------- 128 */ 129func errata_x2_2081180_wa 130 /* Check revision. */ 131 mov x17, x30 132 bl check_errata_2081180 133 cbz x0, 1f 134 135 /* Apply instruction patching sequence */ 136 ldr x0, =0x3 137 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 138 ldr x0, =0xF3A08002 139 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 140 ldr x0, =0xFFF0F7FE 141 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 142 ldr x0, =0x10002001003FF 143 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 144 ldr x0, =0x4 145 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 146 ldr x0, =0xBF200000 147 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 148 ldr x0, =0xFFEF0000 149 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 150 ldr x0, =0x10002001003F3 151 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 152 isb 1531: 154 ret x17 155endfunc errata_x2_2081180_wa 156 157func check_errata_2081180 158 /* Applies to r0p0, r1p0 and r2p0 */ 159 mov x1, #0x20 160 b cpu_rev_var_ls 161endfunc check_errata_2081180 162 163 /* -------------------------------------------------- 164 * Errata Workaround for Cortex X2 Errata #2083908. 165 * This applies to revision r2p0 and is open. 166 * x0: variant[4:7] and revision[0:3] of current cpu. 167 * Shall clobber: x0-x2, x17 168 * -------------------------------------------------- 169 */ 170func errata_cortex_x2_2083908_wa 171 /* Check workaround compatibility. */ 172 mov x17, x30 173 bl check_errata_2083908 174 cbz x0, 1f 175 176 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 177 mrs x1, CORTEX_X2_CPUACTLR5_EL1 178 orr x1, x1, #BIT(13) 179 msr CORTEX_X2_CPUACTLR5_EL1, x1 180 1811: 182 ret x17 183endfunc errata_cortex_x2_2083908_wa 184 185func check_errata_2083908 186 /* Applies to r2p0 */ 187 mov x1, #0x20 188 mov x2, #0x20 189 b cpu_rev_var_range 190endfunc check_errata_2083908 191 192 /* --------------------------------------------------------- 193 * Errata Workaround for Cortex-X2 Errata 2147715. 194 * This applies only to revisions r2p0 and is fixed in r2p1. 195 * Inputs: 196 * x0: variant[4:7] and revision[0:3] of current cpu. 197 * Shall clobber: x0, x1, x17 198 * --------------------------------------------------------- 199 */ 200func errata_x2_2147715_wa 201 /* Compare x0 against revision r2p0 */ 202 mov x17, x30 203 bl check_errata_2147715 204 cbz x0, 1f 205 206 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 207 mrs x1, CORTEX_X2_CPUACTLR_EL1 208 orr x1, x1, CORTEX_X2_CPUACTLR_EL1_BIT_22 209 msr CORTEX_X2_CPUACTLR_EL1, x1 210 2111: 212 ret x17 213endfunc errata_x2_2147715_wa 214 215func check_errata_2147715 216 /* Applies to r2p0 */ 217 mov x1, #0x20 218 mov x2, #0x20 219 b cpu_rev_var_range 220endfunc check_errata_2147715 221 222 /* -------------------------------------------------- 223 * Errata Workaround for Cortex X2 Errata 2216384. 224 * This applies to revisions r0p0, r1p0, and r2p0 225 * and is fixed in r2p1. 226 * x0: variant[4:7] and revision[0:3] of current cpu. 227 * Shall clobber: x0, x1, x17 228 * -------------------------------------------------- 229 */ 230func errata_x2_2216384_wa 231 /* Check workaround compatibility. */ 232 mov x17, x30 233 bl check_errata_2216384 234 cbz x0, 1f 235 236 mrs x1, CORTEX_X2_CPUACTLR5_EL1 237 orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 238 msr CORTEX_X2_CPUACTLR5_EL1, x1 239 240 /* Apply instruction patching sequence */ 241 ldr x0, =0x5 242 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 243 ldr x0, =0x10F600E000 244 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 245 ldr x0, =0x10FF80E000 246 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 247 ldr x0, =0x80000000003FF 248 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 249 isb 250 2511: 252 ret x17 253endfunc errata_x2_2216384_wa 254 255func check_errata_2216384 256 /* Applies to r0p0 - r2p0 */ 257 mov x1, #0x20 258 b cpu_rev_var_ls 259endfunc check_errata_2216384 260 261 /* --------------------------------------------------------------- 262 * Errata Workaround for Cortex-X2 Erratum 2282622. 263 * This applies to revision r0p0, r1p0, r2p0 and r2p1. 264 * It is still open. 265 * Inputs: 266 * x0: variant[4:7] and revision[0:3] of current cpu. 267 * Shall clobber: x0, x1, x17 268 * --------------------------------------------------------------- 269 */ 270func errata_x2_2282622_wa 271 /* Compare x0 against revision r2p1 */ 272 mov x17, x30 273 bl check_errata_2282622 274 cbz x0, 1f 275 276 /* Apply the workaround */ 277 mrs x1, CORTEX_X2_CPUACTLR2_EL1 278 orr x1, x1, #BIT(0) 279 msr CORTEX_X2_CPUACTLR2_EL1, x1 280 2811: 282 ret x17 283endfunc errata_x2_2282622_wa 284 285func check_errata_2282622 286 /* Applies to r0p0, r1p0, r2p0 and r2p1 */ 287 mov x1, #0x21 288 b cpu_rev_var_ls 289endfunc check_errata_2282622 290 291 /* ------------------------------------------------------- 292 * Errata Workaround for Cortex-X2 Erratum 2371105. 293 * This applies to revisions <= r2p0 and is fixed in r2p1. 294 * x0: variant[4:7] and revision[0:3] of current cpu. 295 * Shall clobber: x0-x17 296 * ------------------------------------------------------- 297 */ 298func errata_x2_2371105_wa 299 /* Check workaround compatibility. */ 300 mov x17, x30 301 bl check_errata_2371105 302 cbz x0, 1f 303 304 /* Set bit 40 in CPUACTLR2_EL1 */ 305 mrs x1, CORTEX_X2_CPUACTLR2_EL1 306 orr x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40 307 msr CORTEX_X2_CPUACTLR2_EL1, x1 308 isb 3091: 310 ret x17 311endfunc errata_x2_2371105_wa 312 313func check_errata_2371105 314 /* Applies to <= r2p0. */ 315 mov x1, #0x20 316 b cpu_rev_var_ls 317endfunc check_errata_2371105 318 319 /* ---------------------------------------------------- 320 * Errata Workaround for Cortex-X2 Errata #2768515 321 * This applies to revisions <= r2p1 and is still open. 322 * x0: variant[4:7] and revision[0:3] of current cpu. 323 * Shall clobber: x0-x17 324 * ---------------------------------------------------- 325 */ 326func errata_x2_2768515_wa 327 mov x17, x30 328 bl check_errata_2768515 329 cbz x0, 1f 330 331 /* dsb before isb of power down sequence */ 332 dsb sy 3331: 334 ret x17 335endfunc errata_x2_2768515_wa 336 337func check_errata_2768515 338 /* Applies to all revisions <= r2p1 */ 339 mov x1, #0x21 340 b cpu_rev_var_ls 341endfunc check_errata_2768515 342 343func check_errata_cve_2022_23960 344#if WORKAROUND_CVE_2022_23960 345 mov x0, #ERRATA_APPLIES 346#else 347 mov x0, #ERRATA_MISSING 348#endif 349 ret 350endfunc check_errata_cve_2022_23960 351 352 /* ---------------------------------------------------- 353 * HW will do the cache maintenance while powering down 354 * ---------------------------------------------------- 355 */ 356func cortex_x2_core_pwr_dwn 357 /* --------------------------------------------------- 358 * Enable CPU power down bit in power control register 359 * --------------------------------------------------- 360 */ 361 mrs x0, CORTEX_X2_CPUPWRCTLR_EL1 362 orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 363 msr CORTEX_X2_CPUPWRCTLR_EL1, x0 364#if ERRATA_X2_2768515 365 mov x15, x30 366 bl cpu_get_rev_var 367 bl errata_x2_2768515_wa 368 mov x30, x15 369#endif /* ERRATA_X2_2768515 */ 370 isb 371 ret 372endfunc cortex_x2_core_pwr_dwn 373 374 /* 375 * Errata printing function for Cortex X2. Must follow AAPCS. 376 */ 377#if REPORT_ERRATA 378func cortex_x2_errata_report 379 stp x8, x30, [sp, #-16]! 380 381 bl cpu_get_rev_var 382 mov x8, x0 383 384 /* 385 * Report all errata. The revision-variant information is passed to 386 * checking functions of each errata. 387 */ 388 report_errata ERRATA_X2_2002765, cortex_x2, 2002765 389 report_errata ERRATA_X2_2017096, cortex_x2, 2017096 390 report_errata ERRATA_X2_2058056, cortex_x2, 2058056 391 report_errata ERRATA_X2_2081180, cortex_x2, 2081180 392 report_errata ERRATA_X2_2083908, cortex_x2, 2083908 393 report_errata ERRATA_X2_2147715, cortex_x2, 2147715 394 report_errata ERRATA_X2_2216384, cortex_x2, 2216384 395 report_errata ERRATA_X2_2282622, cortex_x2, 2282622 396 report_errata ERRATA_X2_2371105, cortex_x2, 2371105 397 report_errata ERRATA_X2_2768515, cortex_x2, 2768515 398 report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960 399 report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941 400 401 ldp x8, x30, [sp], #16 402 ret 403endfunc cortex_x2_errata_report 404#endif 405 406func cortex_x2_reset_func 407 mov x19, x30 408 409 /* Disable speculative loads */ 410 msr SSBS, xzr 411 412 /* Get the CPU revision and stash it in x18. */ 413 bl cpu_get_rev_var 414 mov x18, x0 415 416#if ERRATA_DSU_2313941 417 bl errata_dsu_2313941_wa 418#endif 419 420#if ERRATA_X2_2002765 421 mov x0, x18 422 bl errata_cortex_x2_2002765_wa 423#endif 424 425#if ERRATA_X2_2058056 426 mov x0, x18 427 bl errata_cortex_x2_2058056_wa 428#endif 429 430#if ERRATA_X2_2083908 431 mov x0, x18 432 bl errata_cortex_x2_2083908_wa 433#endif 434 435#if ERRATA_X2_2017096 436 mov x0, x18 437 bl errata_x2_2017096_wa 438#endif 439 440#if ERRATA_X2_2081180 441 mov x0, x18 442 bl errata_x2_2081180_wa 443#endif 444 445#if ERRATA_X2_2216384 446 mov x0, x18 447 bl errata_x2_2216384_wa 448#endif 449 450#if ERRATA_X2_2147715 451 mov x0, x18 452 bl errata_x2_2147715_wa 453#endif 454 455#if ERRATA_X2_2282622 456 mov x0, x18 457 bl errata_x2_2282622_wa 458#endif 459 460#if ERRATA_X2_2371105 461 mov x0, x18 462 bl errata_x2_2371105_wa 463#endif 464 465#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 466 /* 467 * The Cortex-X2 generic vectors are overridden to apply errata 468 * mitigation on exception entry from lower ELs. 469 */ 470 adr x0, wa_cve_vbar_cortex_x2 471 msr vbar_el3, x0 472#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 473 474 isb 475 ret x19 476endfunc cortex_x2_reset_func 477 478 /* --------------------------------------------- 479 * This function provides Cortex X2 specific 480 * register information for crash reporting. 481 * It needs to return with x6 pointing to 482 * a list of register names in ascii and 483 * x8 - x15 having values of registers to be 484 * reported. 485 * --------------------------------------------- 486 */ 487.section .rodata.cortex_x2_regs, "aS" 488cortex_x2_regs: /* The ascii list of register names to be reported */ 489 .asciz "cpuectlr_el1", "" 490 491func cortex_x2_cpu_reg_dump 492 adr x6, cortex_x2_regs 493 mrs x8, CORTEX_X2_CPUECTLR_EL1 494 ret 495endfunc cortex_x2_cpu_reg_dump 496 497declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 498 cortex_x2_reset_func, \ 499 cortex_x2_core_pwr_dwn 500