1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x2.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_x2_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_x2 33 34workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 35 ldr x0, =0x6 36 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ 37 ldr x0, =0xF3A08002 38 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ 39 ldr x0, =0xFFF0F7FE 40 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ 41 ldr x0, =0x40000001003ff 42 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ 43workaround_reset_end cortex_x2, ERRATUM(2002765) 44 45check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) 46 47workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 48 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT 49workaround_reset_end cortex_x2, ERRATUM(2017096) 50 51check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) 52 53workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 54 /* Apply instruction patching sequence */ 55 ldr x0, =0x3 56 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 57 ldr x0, =0xF3A08002 58 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 59 ldr x0, =0xFFF0F7FE 60 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 61 ldr x0, =0x10002001003FF 62 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 63 ldr x0, =0x4 64 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 65 ldr x0, =0xBF200000 66 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 67 ldr x0, =0xFFEF0000 68 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 69 ldr x0, =0x10002001003F3 70 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 71workaround_reset_end cortex_x2, ERRATUM(2081180) 72 73check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) 74 75workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 76 /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ 77 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) 78workaround_reset_end cortex_x2, ERRATUM(2083908) 79 80check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 81 82workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 83 /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ 84 sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 85workaround_reset_end cortex_x2, ERRATUM(2147715) 86 87check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 88 89workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 90 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 91 92 /* Apply instruction patching sequence */ 93 ldr x0, =0x5 94 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 95 ldr x0, =0x10F600E000 96 msr CORTEX_X2_IMP_CPUPOR_EL3, x0 97 ldr x0, =0x10FF80E000 98 msr CORTEX_X2_IMP_CPUPMR_EL3, x0 99 ldr x0, =0x80000000003FF 100 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 101workaround_reset_end cortex_x2, ERRATUM(2216384) 102 103check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) 104 105workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 106 /* Apply the workaround */ 107 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) 108workaround_reset_end cortex_x2, ERRATUM(2282622) 109 110check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) 111 112workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941 113 errata_dsu_2313941_wa_impl 114workaround_reset_end cortex_x2, ERRATUM(2313941) 115 116check_erratum_custom_start cortex_x2, ERRATUM(2313941) 117 check_errata_dsu_2313941_impl 118 ret 119check_erratum_custom_end cortex_x2, ERRATUM(2313941) 120 121workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 122 /* Set bit 40 in CPUACTLR2_EL1 */ 123 sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 124workaround_reset_end cortex_x2, ERRATUM(2371105) 125 126check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) 127 128workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 129 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 130 sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) 131 sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) 132workaround_reset_end cortex_x2, ERRATUM(2742423) 133 134check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) 135 136workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 137 /* dsb before isb of power down sequence */ 138 dsb sy 139workaround_runtime_end cortex_x2, ERRATUM(2768515) 140 141check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) 142 143workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471 144 sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47) 145workaround_reset_end cortex_x2, ERRATUM(2778471) 146 147check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1) 148 149add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772 150 151check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1) 152 153workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 154#if IMAGE_BL31 155 /* 156 * The Cortex-X2 generic vectors are overridden to apply errata 157 * mitigation on exception entry from lower ELs. 158 */ 159 override_vector_table wa_cve_vbar_cortex_x2 160#endif /* IMAGE_BL31 */ 161workaround_reset_end cortex_x2, CVE(2022, 23960) 162 163check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 164 165/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 166workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 167 sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46) 168workaround_reset_end cortex_x2, CVE(2024, 5660) 169 170check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1) 171 172 /* ---------------------------------------------------- 173 * HW will do the cache maintenance while powering down 174 * ---------------------------------------------------- 175 */ 176func cortex_x2_core_pwr_dwn 177 /* --------------------------------------------------- 178 * Enable CPU power down bit in power control register 179 * --------------------------------------------------- 180 */ 181 sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 182 183 apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV 184 isb 185 ret 186endfunc cortex_x2_core_pwr_dwn 187 188cpu_reset_func_start cortex_x2 189 /* Disable speculative loads */ 190 msr SSBS, xzr 191 enable_mpmm 192cpu_reset_func_end cortex_x2 193 194 /* --------------------------------------------- 195 * This function provides Cortex X2 specific 196 * register information for crash reporting. 197 * It needs to return with x6 pointing to 198 * a list of register names in ascii and 199 * x8 - x15 having values of registers to be 200 * reported. 201 * --------------------------------------------- 202 */ 203.section .rodata.cortex_x2_regs, "aS" 204cortex_x2_regs: /* The ascii list of register names to be reported */ 205 .asciz "cpuectlr_el1", "" 206 207func cortex_x2_cpu_reg_dump 208 adr x6, cortex_x2_regs 209 mrs x8, CORTEX_X2_CPUECTLR_EL1 210 ret 211endfunc cortex_x2_cpu_reg_dump 212 213declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ 214 cortex_x2_reset_func, \ 215 cortex_x2_core_pwr_dwn 216