1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430 25 /* Disable allocation of splintered pages in the L2 TLB */ 26 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN 27workaround_reset_end cortex_a78c, ERRATUM(1827430) 28 29check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0) 30 31workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440 32 /* Force Atomic Store to WB memory be done in L1 data cache */ 33 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2) 34workaround_reset_end cortex_a78c, ERRATUM(1827440) 35 36check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0) 37 38workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064 39 /* -------------------------------------------------------- 40 * Place the data prefetcher in the most conservative mode 41 * to reduce prefetches by writing the following bits to 42 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 43 * -------------------------------------------------------- 44 */ 45 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7) 46workaround_reset_end cortex_a78c, ERRATUM(2132064) 47 48check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2) 49 50workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638 51 ldr x0, =0x5 52 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 53 ldr x0, =0x10F600E000 54 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 55 ldr x0, =0x10FF80E000 56 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 57 ldr x0, =0x80000000003FF 58 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 59workaround_reset_end cortex_a78c, ERRATUM(2242638) 60 61check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2) 62 63workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749 64 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0 65workaround_reset_end cortex_a78c, ERRATUM(2376749) 66 67check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2) 68 69workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411 70 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40 71workaround_reset_end cortex_a78c, ERRATUM(2395411) 72 73check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) 74 75workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 76 /* dsb before isb of power down sequence */ 77 dsb sy 78workaround_runtime_end cortex_a78c, ERRATUM(2772121) 79 80check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2) 81 82workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484 83 sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) 84workaround_reset_end cortex_a78c, ERRATUM(2779484) 85 86check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2) 87 88check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 89 90workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 91#if IMAGE_BL31 92 /* 93 * The Cortex-A78c generic vectors are overridden to apply errata 94 * mitigation on exception entry from lower ELs. 95 */ 96 override_vector_table wa_cve_vbar_cortex_a78c 97#endif /* IMAGE_BL31 */ 98workaround_reset_end cortex_a78c, CVE(2022, 23960) 99 100cpu_reset_func_start cortex_a78c 101cpu_reset_func_end cortex_a78c 102 103errata_report_shim cortex_a78c 104 105 /* ---------------------------------------------------- 106 * HW will do the cache maintenance while powering down 107 * ---------------------------------------------------- 108 */ 109func cortex_a78c_core_pwr_dwn 110 /* --------------------------------------------------- 111 * Enable CPU power down bit in power control register 112 * --------------------------------------------------- 113 */ 114 sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 115 116 apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 117 118 isb 119 ret 120endfunc cortex_a78c_core_pwr_dwn 121 122 /* --------------------------------------------- 123 * This function provides cortex_a78c specific 124 * register information for crash reporting. 125 * It needs to return with x6 pointing to 126 * a list of register names in ascii and 127 * x8 - x15 having values of registers to be 128 * reported. 129 * --------------------------------------------- 130 */ 131.section .rodata.cortex_a78c_regs, "aS" 132cortex_a78c_regs: /* The ascii list of register names to be reported */ 133 .asciz "cpuectlr_el1", "" 134 135func cortex_a78c_cpu_reg_dump 136 adr x6, cortex_a78c_regs 137 mrs x8, CORTEX_A78C_CPUECTLR_EL1 138 ret 139endfunc cortex_a78c_cpu_reg_dump 140 141declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 142 cortex_a78c_reset_func, \ 143 cortex_a78c_core_pwr_dwn 144