1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24/* -------------------------------------------------- 25 * Errata Workaround for A78C Erratum 2132064. 26 * This applies to revisions r0p1 and r0p2 of A78C 27 * and is still open. 28 * Inputs: 29 * x0: variant[4:7] and revision[0:3] of current cpu. 30 * Shall clobber: x0-x17 31 * -------------------------------------------------- 32 */ 33func errata_a78c_2132064_wa 34 /* Compare x0 against revisions r0p0 - r0p1 */ 35 mov x17, x30 36 bl check_errata_2132064 37 cbz x0, 1f 38 39 /* -------------------------------------------------------- 40 * Place the data prefetcher in the most conservative mode 41 * to reduce prefetches by writing the following bits to 42 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 43 * -------------------------------------------------------- 44 */ 45 mrs x0, CORTEX_A78C_CPUECTLR_EL1 46 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT6 47 orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT7 48 msr CORTEX_A78C_CPUECTLR_EL1, x0 49 isb 501: 51 ret x17 52endfunc errata_a78c_2132064_wa 53 54func check_errata_2132064 55 /* Applies to revisions r0p1 and r0p2. */ 56 mov x1, #CPU_REV(0, 1) 57 mov x2, #CPU_REV(0, 2) 58 b cpu_rev_var_range 59endfunc check_errata_2132064 60 61func check_errata_cve_2022_23960 62#if WORKAROUND_CVE_2022_23960 63 mov x0, #ERRATA_APPLIES 64#else 65 mov x0, #ERRATA_MISSING 66#endif 67 ret 68endfunc check_errata_cve_2022_23960 69 70 /* ------------------------------------------------- 71 * The CPU Ops reset function for Cortex-A78C 72 * ------------------------------------------------- 73 */ 74func cortex_a78c_reset_func 75 mov x19, x30 76 bl cpu_get_rev_var 77 mov x18, x0 78 79#if ERRATA_A78C_2132064 80 mov x0, x18 81 bl errata_a78c_2132064_wa 82#endif 83 84#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 85 /* 86 * The Cortex-A78c generic vectors are overridden to apply errata 87 * mitigation on exception entry from lower ELs. 88 */ 89 adr x0, wa_cve_vbar_cortex_a78c 90 msr vbar_el3, x0 91#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 92 93 isb 94 ret x19 95endfunc cortex_a78c_reset_func 96 97 /* ---------------------------------------------------- 98 * HW will do the cache maintenance while powering down 99 * ---------------------------------------------------- 100 */ 101func cortex_a78c_core_pwr_dwn 102 /* --------------------------------------------------- 103 * Enable CPU power down bit in power control register 104 * --------------------------------------------------- 105 */ 106 mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 107 orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 108 msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 109 isb 110 ret 111endfunc cortex_a78c_core_pwr_dwn 112 113#if REPORT_ERRATA 114/* 115 * Errata printing function for Cortex A78C. Must follow AAPCS. 116 */ 117func cortex_a78c_errata_report 118 stp x8, x30, [sp, #-16]! 119 120 bl cpu_get_rev_var 121 mov x8, x0 122 123 /* 124 * Report all errata. The revision-variant information is passed to 125 * checking functions of each errata. 126 */ 127 report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 128 report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 129 130 ldp x8, x30, [sp], #16 131 ret 132endfunc cortex_a78c_errata_report 133#endif 134 135 /* --------------------------------------------- 136 * This function provides cortex_a78c specific 137 * register information for crash reporting. 138 * It needs to return with x6 pointing to 139 * a list of register names in ascii and 140 * x8 - x15 having values of registers to be 141 * reported. 142 * --------------------------------------------- 143 */ 144.section .rodata.cortex_a78c_regs, "aS" 145cortex_a78c_regs: /* The ascii list of register names to be reported */ 146 .asciz "cpuectlr_el1", "" 147 148func cortex_a78c_cpu_reg_dump 149 adr x6, cortex_a78c_regs 150 mrs x8, CORTEX_A78C_CPUECTLR_EL1 151 ret 152endfunc cortex_a78c_cpu_reg_dump 153 154declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 155 cortex_a78c_reset_func, \ 156 cortex_a78c_core_pwr_dwn 157